HSP45314VI Ver la hoja de datos (PDF) - Intersil

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HSP45314VI

CommLink™ Direct Digital Synthesizer

Intersil 

HSP45314

Timing Diagrams (Continued)

ONE CLK RISING EDGE

REQUIRED WHILE RESET LOW

CLK

RESET

tRS

tRL = 11 CLK RISING EDGES

ANALOG OUT

PREVIOUS REGISTER VALUES

RESET REGISTER VALUES

FIGURE 4. RESET TIMING AND LATENCY

CLK

ENOFR

ANALOG OUT

tEH

tES

CENTER FREQUENCY ONLY

tEL = 14 CLK RISING EDGES

CENTER + OFFSET

CENTER ONLY

CENTER

+ OFFSET

FIGURE 5. ENOFR (ENABLE OFFSET FREQUENCY REGISTER) TIMING AND LATENCY (RESET = HIGH)

Pin Descriptions

PIN NO.

PIN NAME

44-48, 1-3

C(7:0)

42

WR

40

35-38

WE

A(3:0)

6

CLK

8

RESET

30

DGND

27

DGND

32

DGND

9

UPDATE

TYPE

Input

Input

Input

Input

Clock

Input

(Input)

(Input)

(Input)

Input

PIN DESCRIPTION

8-bit Processor Input Data Bus. C7 is the MSB. Data is written to the control register selected on

A(3:0) on the rising edge of WR when WE is active.

Write Clock For The Processor Interface. Parallel data is clocked into the chip on the rising edge

of WR.

Write Enable. Active low. WE must be active when writing data to the chip.

Processor Interface Address Bus. These pins select the destination register for data on the

C(7:0) bus. A3 is the MSB.

NCO and DAC Clock. The phase accumulator and DAC output update on the rising edge of this

clock. CLK can be asynchronous to the WR clock.

Reset. Active Low. Resets control registers to their default states (see register description table)

and zeroes the feedback in the phase accumulator. UPDATE must be low for Reset to occur.

Connect to DGND. Future serial clock input.

Connect to DGND. Future serial data input.

Connect to DGND. Future serial sync input.

Active Low. Updates the active control registers only. It has no effect on the ENOFR or PH(1:0)

pins. This pin is provided for updating an entire frequency word at once rather than byte by byte.

12

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