HC68T1M2Z(2006) Ver la hoja de datos (PDF) - Intersil
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HC68T1M2Z Datasheet PDF : 24 Pages
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Read/Write Data (See Figure 10)
Read/Write data follows the Address/Control byte.
BIT 7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
CE
SCK (NOTE)
MOSI
D7
D6
D5
D4
D3
D2
D1
D0
MISO
D7
D6
D5
D4
D3
D2
D1
D0
NOTE: SCK can be either polarity.
FIGURE 10. READ/WRITE DATA TRANSFER WAVEFORMS
Watchdog Reset (See Figure 11)
When watchdog operation is selected, CE must be toggled
periodically or a CPU reset will be outputted.
SERVICE
TIME
SERVICE
TIME
CE
SCK
CPUR
FIGURE 11. WATCHDOG OPERATION WAVEFORMS
Address And Data
Data transfers can occur one byte at a time (Figure 12) or in
a multibyte burst mode (Figure 13). After the Real-Time
Clock enabled, an Address/Control word is sent to set the
CLOCK or RAM and select the type of operation (i.e., Read
or Write). For a single-byte Read or Write, one byte is
transferred to or from the Clock Register or RAM location
specified in the Address/Control byte and the Real-Time
Clock is then disabled. Write cycle causes the latched Clock
Register or RAM address to automatically increment.
Incrementing continues after each transfer until the device is
disabled. After incrementing to 1FH the address will “wrap”
to 00H and continue. Therefore, when the RAM is selected
the address will “wrap” to 00H and when the clock is
selected the address will “wrap” 20H.
15
FN1547.7
March 17, 2006
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