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74VHC4046

CMOS Phase Lock Loop

Fairchild Semiconductor 

Detailed Circuit Description (Continued)

FIGURE 5. Logic Diagram for Phase Comparator II

FIGURE 6. Typical Phase Comparator II Output Waveforms

If the VCO leads the signal then when the leading edge of

the VCO is seen the output of the phase comparator goes

LOW. This discharges the loop filter until the leading edge

of the signal is detected at which time the output 3-STATEs

itself again. This has the effect of slowing down the VCO to

again make the rising edges of both waveform coincident.

As one can see when the PLL is locked the output of phase

comparator II will be almost always 3-STATE except for

minor corrections at the leading edge of the waveforms.

When the detector is 3-STATE the phase pulse output is

HIGH. This output can be used to determine when the PLL

is in the locked condition.

When the PLL is out of lock the VCO will be running either

slower or faster than the signal input. If it is running slower

the phase detector will see more signal rising edges and so

the output of the phase comparator will be high a majority

of the time, raising the VCO’s frequency. Conversely, if the

VCO is running faster than the signal the output of the

detector will be low most of the time and the VCO’s output

frequency will be decreased.

This detector has several interesting characteristics. Over

the entire VCO frequency range there is no phase differ-

ence between the comparator input and the signal input.

The lock range of the PLL is the same as the capture

range. Minimal power is consumed in the loop filter since in

lock the detector output is a high impedance. Also when no

signal is present the detector will see only VCO leading

edges, and so the comparator output will stay low forcing

the VCO to fMIN operating frequency.

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