
TLP117
TEST CIRCUIT 1 : VOL
IF 1
→
6
VCC
5
↑
3
GND 4
SHIELD
0.1μF
VOL IOL
V↑
TEST CIRCUIT 2 : VOH
1
VCC
3
6
VCC
5
V VOH ↑ IOH
VCC
GND 4
0.1μF
SHIELD
TEST CIRCUIT 3 : ICCL
IF
→
1
6
ICCL
VCC
A
↑
5 0.1μF
VCC
3
GND 4
SHIELD
TEST CIRCUIT 4: ICCH
1
6
ICCH
VCC
A
5 0.1μF
VCC
3
4
GND
SHIELD
TEST CIRCUIT 5 : tpHL , tpLH
INPUT MONITORING NODE
VIN=0↔5V(P.G)
(f=25MHz , duty=50%)
VCC
*CL=15pF
CIN =22pF
SHIELD
RIN=360Ω
GND
tr=4.5ns
0.1μF
Vo
MONITORING
NODE
VCC
*CL=15pF
VIN 10%
VO
90%
tf
CL is capacitance of the probe and JIG.
(P.G) : Pulse Generator
tpHL
tf=4.5ns
50%
VL=0V
tr
GND
VOH
90%
50%
10% VOL
tpLH
5
2010-04-02