TLE 6711
Circuit Description
is HIGH the system enable goes active HIGH with the first valid watchdog trigger pulse at pin WDI. The SEN output
goes LOW immediately if a pretrigger, a missing trigger or a power down reset occurs.
TWD = 128*tCYL
tSR = 64*tCYL
tWDR = 64*tCYL
tCW=32*tCYL
tOW=32*tCYL
definition
closed window
open window
definition
worst case
reset start delay time after window
watchdog timeout
reset duration time after window
watchdog time-out
tECW
t EOW = end of open window
fOSC=fOSCmax
t (CW+OW)min = ( tCW+ tOW ) (1 - ∆)
fOSC=fOSCmin
t CWmax= tCW (1+∆ )
t WD
t OWmin
Figure 5 Window Watchdog Definitions 1
Example with:
tCYL=1ms
∆=10% (oscillator deviation)
t(CW+OW)min =(tCW+tOW)*(1-∆)=
=(32+32)x0,9= 57,6ms
tCWmax= tCW(1+∆)=32*1,1=35,2ms
Closed window Open window
Watchdog
trigger signal
Open window Closed window
WDI
Valid
WDI
Indifferent
WDI
Not valid
t ECW
= Watchdog decoder sample point
t EOW
AET02952
Figure 6 Window Watchdog Definitions 2
Data Sheet
9
Rev. 3.4, 2007-08-16