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T83C5102XXX-ICFCL

8-bit Low Pin Count Microcontrollers

Atmel Corporation 

T8xC5101/02

T8xC5101/02 Serial

I/O Port

Framing Error Detection

The serial I/O port in the T8xC5101/02 family is compatible with the serial I/O port in the

80C52. It provides both synchronous and asynchronous communication modes. It oper-

ates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-

duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur

simultaneously and at different baud rates.

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 7).

Figure 7. Framing Error Block Diagram

SM0/FE SM1 SM2 REN TB8 RB8 TI

RI SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD = 0)

SMOD1SMOD0 -

POF GF1 GF0 PD IDL

To UART framing error control

PCON (87h)

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See ) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 8. and Figure 9.).

Figure 8. UART Timings in Mode 1

RXD

D0 D1 D2 D3 D4 D5 D6 D7

RI

SMOD0=X

Start

bit

Data byte

Stop

bit

FE

SMOD0=1

19

4233H–8051–02/08

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