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SY89828LHYTR

3.3V 1GHz DUAL 1:10 PRECISION LVDS FANOUT BUFFER/TRANSLATOR WITH 2:1 INPUT MUX

Micrel 

Micrel, Inc.

Precision Edge®

SY89828L

AC ELECTRICAL CHARACTERISTICS(NOTE 1)

VCC = 3.3V ±10%, TA = –40°C to +85°C, unless noted.

Symbol

Parameter

Condition

fMAX

tPHL

tPLH

Maximum Toggle Frequency

Differential Propagation Delay

Note 3

Note 2

LVPECL Input: 150mV

LVPECL Input: 800mV

LVDS Input: 100mV

LVDS Input: 400mV

tSWITCHOVER

tS(OE)

tH(OE)

tSKEW

Clock Input Switchover

Output Enable Set-Up Time

Output Enable Hold Time

Within Device Skew

CLK_SEL to Valid Output

Note 4

Note 4

Note 5

tJITTER

tr, tf

Part-to-Part Skew

Cycle-to-Cycle

Total Jitter

Output Rise/Fall Times

(20% to 80%)

Note 6

Note 7

Note 8

0°C to +85°C

–40°C

Min

1.0

0.950

0.80

1.10

0.950

1.0

0.5

200

Typ

1.15

1.0

1.35

1.20

1.55

25

35

<1

290

Max

1.45

1.3

1.60

1.450

1.85

50

75

400

<1

2

400

Units

GHz

ns

ns

ns

ns

ns

ns

ns

ps

ps

ps

psRMS

psPP

ps

Note 1.

Note 2.

Note 3.

Note 4.

Note 5.

Note 6.

Note 7.

Note 8.

100Ω termination between Q and /Q outputs. Airflow ≥300lfpm, or exposed pad soldered to ground plane.

fMAX is defined as the maximum toggle frequency, measured with a 750mV LVPECL input or 350mV LVDS input. Outut swing is > 200mV.

Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential

output signals.

Set-up and hold time applies to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications,

set-up and hold time does not apply. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH to LOW transition ensures

outputs remain disabled during the next clock cycle. OE LOW to HIGH transition enables normal operation of the next input clock.

The within-device skew is defined as the worst case difference between any two similar delay paths within a single device identical input transition,

operating at the same voltage and temperature.

The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage

and temperature. Part-to-part skew is the total skew difference; pin-to-pin skew + part-to-part skew.

Cycle-to-cycle jitter definition: The variation period between adjacent cycles over a random sample of adjacent cycle pairs. TJITTER_CC = Tn –Tn+1

where T is the time between rising edges of the output signal.

Total jitter definition: with an ideal clock input, no more than one output edge in 1012 output edges will deviate by more than the specified peak-

to-peak jitter value.

M9999-012208

hbwhelp@micrel.com or (408) 955-1690

8

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