STM817M Ver la hoja de datos (PDF) - STMicroelectronics

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STM817M

5 V supervisor with battery switchover

STMicroelectronics 

STM690A/692A/703/704/802/805/817/818/819

Operation

2.5

Chip-enable gating (STM818 only)

Internal gating of the chip-enable (E) signal prevents erroneous data from corrupting the

external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series

transmission gate from E to ECON (see Figure 11). During normal operation (reset not

asserted), the E transmission gate is enabled and passes all E transitions. When reset is

asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS

RAM. The short propagation delay from E to ECON enables the STM818 to be used with

most µPs. If E is low when reset asserts, ECON remains low for typically 15 µs (or until E

goes high) to permit the current WRITE cycle to complete. Connect E to VSS if unused.

2.6

Chip-enable input (STM818 only)

The chip-enable transmission gate is disabled and E is high impedance (disabled mode)

while reset is asserted. During a power-down sequence when VCC passes the reset

threshold, the chip-enable transmission gate disables and E immediately becomes high

impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable

transmission gate will disable 15 µs after reset asserts (see Figure 12). This permits the

current WRITE cycle to complete during power-down.

Any time a reset is generated, the chip-enable transmission gate remains disabled and E

remains high impedance (regardless of E activity) for the reset time-out period. When the

chip-enable transmission gate is enabled, the impedance of E appears as a 40 Ω resistor in

series with the load at ECON. The propagation delay through the chip-enable transmission

gate depends on VCC, the source impedance of the drive connected to E, and the loading

on ECON. The chip-enable propagation delay is production tested from the 50% point on E to

the 50% point on ECON using a 50 Ω driver and a 50 pF load capacitance (see Figure 39).

For minimum propagation delay, minimize the capacitive load at ECON and use a low-output

impedance driver.

2.7

Chip-enable output (STM818 only)

When the chip-enable transmission gate is enabled, the impedance of ECON is equivalent to

a 40 Ω resistor in series with the source driving E. In the disabled mode, the transmission

gate is off and an active pull-up connects ECON to VOUT (see Figure 11). This pull-up turns

off when the transmission gate is enabled.

Figure 11. Chip-enable gating

VCC

VRST

E

COMPARE

trec

Generator

ECON OUTPUT

CONTROL

RST

VOUT

ECON

AI08802

Doc ID 10522 Rev 10

15/43

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