STK14C88-C45I Ver la hoja de datos (PDF) - Cypress Semiconductor
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STK14C88-C45I Datasheet PDF : 20 Pages
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STK14C88
SRAM Read Cycles #1 and #2
(VCC = 5.0 V ± 10%)[4]
Symbols
NO.
#1, #2
Alt.
Parameter
STK14C88-25 STK14C88-35 STK14C88-45
Unit
Min Max Min Max Min Max
1
tELQV
tACS
Chip Enable Access Time
–
25
–
35
–
45 ns
2 tAVAV[6], tELEH[6]
tRC
Read Cycle Time
25
35
–
45
–
ns
3
tAVQV7
tAA
Address Access Time
–
25
–
35
–
45 ns
4
tGLQV
5
tAXQX[7]
6
tELQX
7
tEHQZ[8]
8
tGLQX
tOE
tOH
tLZ
tHZ
tOLZ
Output Enable to Data Valid
–
Output Hold after Address Change 5
Address Change or Chip Enable to 5
Output Active
Address Change or Chip Disable to –
Output Inactive
Output Enable to Output Active
0
10
–
–
10
–
–
15
–
s 5
–
5
n 5
–
5
sig –
13
–
De0
–
0
20
–
–
15
–
ns
ns
ns
ns
ns
9
10
11
tGHQZ[8]
w tELICCH[5]
e tEHICCL[5]
tOHZ
Output Disable to Output Inactive
–
10
–
tPA
Chip Enable to Power Active
0
–
0
tPS
Chip Disable to Power Standby
–
25
d for N ADDRESS
nde DQ (DATA OUT)
Figure 4. SRAM Read Cycle 1: Address Controlled [6, 7]
5
tAXQX
2
tAVAV
3
tAVQV
DATA VALID
me Figure 5. SRAM Read Cycle 2: E and G Controlled [6]
com 2
29
e1
6
Not R 3
13
0
35
–
11
7
15 ns
–
ns
45 ns
9
4
8
10
Notes
6. W and HSB must be high during SRAM read cycles.
7. I/O state assumes E and G < VIL and W VIH; device is continuously selected.
8. Measured ± 200 mV from steady state output voltage.
Document Number: 001-52038 Rev. *C
Page 6 of 20
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