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STK14C88-3NF35ITR

32Kx8 AutoStore nvSRAM

Simtek Corporation 

STK14C88-3

HSB OPERATION

The STK14C88-3 provides the HSB pin for control-

ling and acknowledging the STORE operations. The

HSB pin can be used to request a hardware STORE

cycle. When the HSB pin is driven low, the

STK14C88-3 will conditionally initiate a STORE oper-

ation after tDELAY; an actual STORE cycle will only

begin if a WRITE to the SRAM took place since the

last STORE or RECALL cycle. The HSB pin has a

very resistive pullup and is internally driven low to

indicate a busy condition while the STORE (initiated

by any means) is in progress. Pull up this pin with an

external 10K ohm resistor to VCAP if HSB is used as

a driver.

SRAM READ and WRITE operations that are in

progress when HSB is driven low by any means are

given time to complete before the STORE operation

is initiated. After HSB goes low, the STK14C88-3

will continue SRAM operations for tDELAY. During tDELAY,

multiple SRAM READ operations may take place. If a

WRITE is in progress when HSB is pulled low it will

be allowed a time, tDELAY, to complete. However, any

SRAM WRITE cycles requested after HSB goes low

will be inhibited until HSB returns high.

The HSB pin can be used to synchronize multiple

STK14C88-3s while using a single larger capacitor.

To operate in this mode the HSB pin should be con-

nected together to the HSB pins from the other

STK14C88-3s. An external pull-up resistor to +3.3V

is required since HSB acts as an open drain pull-

down. The VCAP pins from the other STK14C88-3

parts can be tied together and share a single capac-

itor. The capacitor size must be scaled by the num-

ber of devices connected to it. When any one of the

STK14C88-3s detects a power loss and asserts

HSB, the common HSB pin will cause all parts to

request a STORE cycle (a STORE will take place in

those STK14C88-3s that have been written since

the last nonvolatile cycle).

During any STORE operation, regardless of how it

was initiated, the STK14C88-3 will continue to drive

the HSB pin low, releasing it only when the STORE is

complete. Upon completion of the STORE operation

the STK14C88-3 will remain disabled until the HSB

pin returns high.

If HSB is not used, it should be left unconnected.

BEST PRACTICES

nvSRAM products have been used effectively for

over 15 years. While ease-of-use is one of the prod-

uct’s main system values, experience gained work-

ing with hundreds of applications has resulted in the

following suggestions as best practices:

• The non-volatile cells in an nvSRAM are pro-

grammed on the test floor during final test and

quality assurance. Incoming inspection routines

at customer or contract manufacturer’s sites will

sometimes reprogram these values. Final NV pat-

terns are typically repeating patterns of AA, 55,

00, FF, A5, or 5A. End product’s firmware should

not assume an NV array is in a set programmed

state. Routines that check memory content val-

ues to determine first time system configuration,

cold or warm boot status, etc. should always pro-

gram a unique NV pattern (e.g., complex 4-byte

pattern of 46 E6 49 53 hex or more random

bytes) as part of the final system manufacturing

test to ensure these system routines work consis-

tently.

• Power up boot firmware routines should rewrite

the nvSRAM into the desired state (autostore

enabled, etc.). While the nvSRAM is shipped in a

preset state, best practice is to again rewrite the

nvSRAM into the desired state as a safeguard

against events that might flip the bit inadvertently

(program bugs, incoming inspection routines,

etc.).

• The Vcap value specified in this datasheet

includes a minimum and a maximum value size.

Best practice is to meet this requirement and not

exceed the max Vcap value because the nvSRAM

internal algorithm calculates Vcap charge time

based on this max Vcap value. Customers that

want to use a larger Vcap value to make sure

there is extra store charge and store time should

discuss their Vcap size selection with Simtek to

understand any impact on the Vcap voltage level

at the end of a tRECALL period.

Document Control #ML0015 Rev 2.0

12

Feb, 2008

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