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SC483

Dual Synchronous Buck Pseudo Fixed Frequency Power Supply Controller

Semtech Corporation 

SC483

POWER MANAGEMENT

Electrical Characteristics (Cont.)

Test Conditions: VBAT = 15V, EN/PSV1=EN/PSV2 = 5V, VCCA1 = VDDP1 = VCCA2 = VDDP2 = 5V, VOUT1 = VOUT2 =1.25V, RTON1 = RTON2 = 1MΩ

Parameter

Conditions

25°C

-40°C to 125°C

Units

Min Typ Max Min Max

Fault Protection (Cont.)

PGD Fault Delay

FB forced outside PGD window

5

VCCA Undervoltage Threshold Falling (100mV Hysteresis )

4.0

µs

3.7

4.3

V

Over Temperature Lockout

Inputs/Outputs

Logic Input Low Voltage

Logic Input High Voltage

Logic Input High Voltage

EN/PSV Input Resistance

Soft Start

Soft-Start Ramp Time

10°C Hysteresis

EN/PSV low

EN High, PSV low (Floating)

EN/PSV high

R Pullup to VCCA

R Pulldown to VSSA

EN/PSV high to PGD high

165

°C

1.2

V

2.0

V

3.1

V

1.5

MΩ

1.0

440

clks(3)

Under-Voltage Blank Time

EN/PSV high to UV high

440

Gate Drivers

Shoot-Through Delay (4)

DH or DL rising

30

DL Pull-Down Resistance

DL low

0.8

DL Sink Current

DL = 2.5V

3.1

DL Pull-Up Resistance

DL high

2

DL Source Current

DL = 2.5V

1.3

DH Pull-Down Resistance

DH low, BST - LX = 5V

2

DH Pull-Up Resistance(5)

DH high, BST - LX = 5V

2

DH Sink/Source Current

DH = 2.5V

1.3

clks(3)

ns

1.6

Ω

A

4

Ω

A

4

Ω

4

Ω

A

Notes:

(1) When the inductor is in continuous and discontinuous conduction mode, the output voltage will have a DC

regulation level higher than the error-comparator threshold by 50% of the ripple voltage.

(2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-

side MOSFET. These values guaranteed by the ILIM Source Current and Current Comparator Offset tests.

(3) clks = Switching cycles.

(4) Guaranteed by design. See Shoot-Through Delay Timing Diagram on Page 6.

(5) Semtech’s SmartDriverTM FET drive first pulls DH high with a pullup resistance of 10Ω (typ.) until LX = 1.5V (typ.).

At this point, an additional pullup device is activated, reducing the resistance to 2Ω (typ.). This negates the need for

an external gate or boost resistor.

 2005 Semtech Corp.

4

www.semtech.com

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