SC1403(2002) Ver la hoja de datos (PDF) - Semtech Corporation
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SC1403 Datasheet PDF : 30 Pages
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SC1403
POWER MANAGEMENT
Functional Information
PRELIMINARY
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Resistance
(ohm)
Deviation
from Vref =
2.4920V
511 2.67K 49.9K 255K 1Meg
8.3mV 3.1mV 0.5mV 0.3mV 0mV
Current Sense (CSH, CSL)
The output current of the power supply is sensed as the voltage
drop across an external resistor between CSH and CSL pins. Over-
current is detected when the current sense voltage exceeds +/-
50mV. A positive over-current will turn off the high-side driver; a
negative over-current will turn off the low-side driver, each on a
cycle by cycle basis.
Oscillator
SHDN ON3 ON5 MODE DESCRIPTION
Low
X
X
Shut-
Minimum bias
down
current
High Low Low Standby VREF and VL
regulator
enable
High High High
Run
Mode
Both SMPS
Running
Output Voltage Selection
If FB is connected to ground, internal resistors setup 3.3V and 5V
output voltages. If external resistors are used, the internal feedback
is disabled and the output is regulated based on 2.5V reference at
the FB pin. (see comment in the application design section).
When the SYNC pin is set high the oscillator runs at 300KHz;
when SYNC is set low the frequency is 200KHz. The oscillator can
also be synchronized to the falling edge of a clock on the SYNC pin
with a frequency between 240KHz and 350KHz. In general,
200KHz operation is used for highest efficiency, and the 300KHz
for minimum output ripple and/or smaller filter components.
Fault Protection
In addition to cycle-by-cycle current limit, the SC1403 monitors
over-temperature, and output over-voltage and under-voltage
conditions. The over-temperature detect will shut the part down if
the die temperature exceeds 150°C with 10°C of hysteresis.
If either SMPS output is more than 10% above its nominal value,
both SMPS are latched off and synchronous rectifiers are latched
on. To prevent the output from ringing below ground in a fault
condition, a 1A Schottky diode should be placed across each output.
Two different levels of undervoltage are detected. If the output
falls 10% below its nominal output, the RESET output is pulled
low.If the output falls 25% below its nominal output following a
start-up delay, both SMPS are latched off. Both of the latched fault
modes persist until SHDN or RUN/ON3 is toggled or the V+ input is
brought below 1V.
Power up Controls and Soft Start
The user has control of the SC1403 RESET# by setting the SEQ,
ON3 and ON5 pins as described in the following table.
Each SMPS contains its own counter and DAC to gradually increase
the current limit at startup to prevent surge currents. The current
limit is increased from 0, 20%, 40%, 60%, 80%, to 100% linearly
over the course of 512 switching cycles.
A RESET# output is also generated at startup. The RESET# pin is
held low for 32K switching cycles. Another timer is used to enable
the undervoltage protection. The undervoltage protection circuitry
is enabled after 6144 switching cycles at which time the SMPS
should be in regulation.
When SEQ is set to REF, the RESET# pin only monitors the 3.3V
SMPS in regulation and the 5V SMPS is ignored.
Applications Information
Reference Circuit Design
Introduction
Shutdown and Operating Modes
Holding the SHDN pin low disables the SC1403, reducing the V+
input current to less than 10uA. When SHDN goes high, the part
enters a standby mode where the VL regulator and VREF are
enabled. Turning on either SMPS will put the SC1403 in run mode.
The SC1403 is a versatile dual switching regulator adjustable
from 2.5V to 5.5V with fixed 5V and 3.3V modes. In addition,
there is an on-chip 5V linear regulator capable of supplying 50mA
output current. The SC1403 is designed for notebook applications
but has applications where high efficiency, small package and low
cost are required.
2002 Semtech Corp.
10
www.semtech.com
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