C164CI Ver la hoja de datos (PDF) - Infineon Technologies
Número de pieza
componentes Descripción
fabricante
C164CI Datasheet PDF : 79 Pages
| |||
C164CI/SI
C164CL/SL
Functional Description
The architecture of the C164CI combines advantages of both RISC and CISC
processors and of advanced peripheral subsystems in a very well-balanced way. In
addition the on-chip memory blocks allow the design of compact systems with maximum
performance.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the C164CI.
Note: All time specifications refer to a CPU clock of 25 MHz
(see definition in the AC Characteristics section).
ProgMem
ROM: 48/64
OTP: 64
KByte
XRAM
2 KByte
32
Instr. / Data
16
C166-Core
CPU
16
Data
16
Data
IRAM
Internal
RAM
2 KByte
External Instr. / Data
PEC
Interrupt Controller 16-Level
Priority
16
Interrupt Bus
Osc / PLL
XTAL
RTC WDT
16
Peripheral Data Bus
CAN
Rev 2.0B active
ADC ASC0 SSC GPT1
CCOM2 CCOM6
EBC
10-Bit (USART) (SPI)
T2
8
Channels
T3
T7
T12
T8
T13
6
XBUS Control
T4
16
External Bus
Control
BRGen BRGen
Port 0
Port 5
Port 3
Port 8
16
8
9
4
MCB04323_4ci
Figure 3 Block Diagram
The program memory, the internal RAM (IRAM) and the set of generic peripherals are
connected to the CPU via separate buses. A fourth bus, the XBUS, connects external
resources as well as additional on-chip resoures, the X-Peripherals (see Figure 3).
The XBUS resources (XRAM, CAN) of the C164CI can be enabled or disabled during
initialization by setting the general X-Peripheral enable bit XPEN (SYSCON.2). Modules
that are disabled consume neither address space nor port pins.
Data Sheet
11
V2.0, 2001-05
Share Link: 