S5L9291X01-T0R0 Ver la hoja de datos (PDF) - Samsung

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S5L9291X01-T0R0

DIGITAL SIGNAL PROCESSOR

Samsung 

DIGITAL SIGNAL PROCESSOR

S5L9291X

EDO-DRAM, FAST-PAGE DRAM INTERFACE TIMING

Read Cycle

RAS

CAS

ADDR

2T

1T

1T

ROW ADDRESS

1T = 59ns/2 at Bus X4

1T = 59ns at Bus X8, X16

4T

2T

2T

4T

COLUMN ADDRESS

WE

DATA[3:0]

1T

1T

DATA-OUT

Don't Care

OE = GND

Write Cycle

RAS

CAS

ADDR

1T = 59ns/2 at Bus X4

1T = 59ns at Bus X8, X16

4T

2T

2T

2T

1T

1T

ROW ADDRESS

4T

COLUMN ADDRESS

WE

DATA[3:0]

2T

2T

DATA-IN

Don't Care

OE = GND

11

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