PSD822F2-70J Ver la hoja de datos (PDF) - STMicroelectronics

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PSD822F2-70J

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD835G2

The

PSD835G2

Functional

Blocks

(cont.)

PSD8XX Family

9.2.2.2 The Product Term Allocator

The CPLD has a Product Term Allocator. The PSDsoft uses the Allocator to borrow and

place product terms from one Micro⇔Cell to another. The following list summarizes how

product terms are allocated:

• McellA0-7 all have three native product terms and may borrow up to six more

• McellB0-3 all have four native product terms and may borrow up to five more

• McellB4-7 all have four native product terms and may borrow up to six more.

Each Micro⇔Cell may only borrow product terms from certain other Micro⇔Cells. Product

terms already in use by one Micro⇔Cell will not be available for a different Micro⇔Cell.

If an equation requires more product terms than what is available to it, then “external”

product terms will be required, which will consume other OMCs. If external product terms

are used, extra delay will be added for the equation that required the extra product terms.

This is called product term expansion. PSDsoft will perform this expansion as needed.

9.2.2.3 Loading and Reading the Output Micro⇔Cells (OMCs)

The OMCs occupy a memory location in the MCU address space, as defined by the

CSIOP (refer to the I/O section). The flip-flops in each of the 16 OMCs can be loaded from

the data bus by a microcontroller. Loading the OMCs with data from the MCU takes priority

over internal functions. As such, the preset, clear, and clock inputs to the flip-flop can be

overridden by the MCU. The ability to load the flip-flops and read them back is useful in

such applications as loadable counters and shift registers, mailboxes, and handshaking

protocols. Data is loaded to the OMCs on the trailing edge of the WR signal .

9.2.2.4 The OMC Mask Register

There is one Mask Register for each of the two groups of eight OMCs. The Mask Registers

can be used to block the loading of data to individual OMCs. The default value for the

Mask Registers is 00h, which allows loading of the OMCs. When a given bit in a Mask

Register is set to a ‘1’, the MCU will be blocked from writing to the associated OMC. For

example, suppose McellA0-3 are being used for a state machine. You would not want a

MCU write to McellA to overwrite the state machine registers. Therefore, you would want to

load the Mask Register for McellA (Mask Micro⇔Cell A) with the value 0Fh.

9.2.2.5 The Output Enable of the OMC

The OMC can be connected to an I/O port pin as a PLD output. The output enable of each

Port pin driver is controlled by a single product term from the AND array, ORed with the

Direction Register output. The pin is enabled upon power up if no output enable equation

is defined and if the pin is declared as a PLD output in PSDsoft.

If the OMC output is declared as an internal node and not as a Port pin output in the

PSDabel file, then the Port pin can be used for other I/O functions. The internal node

feedback can be routed as an input to the AND array.

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