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PSD822F2-70J

Configurable Memory System on a Chip for 8-Bit Microcontrollers

STMicroelectronics 

PSD8XX Family

The

PSD835G2

Functional

Blocks

(cont.)

PSD835G2

9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces

9.1.3.2.1 Separate Space Modes

Code memory space is separated from data memory space. For example, the PSEN

signal is used to access the program code from the main Flash Memory, while the RD

signal is used to access data from the secondary Flash memory, SRAM and I/O Ports.

This configuration requires the VM register to be set to 0Ch.

9.1.3.2.2 . Combined Space Modes

The program and data memory spaces are combined into one space that allows the main

Flash Memory, secondary Flash memory, and SRAM to be accessed by either PSEN or

RD. For example, to configure the main Flash memory in combined space mode, bits 2

and 4 of the VM register are set to “1”.

9.1.3.3 80C51XA Memory Map Example

See Application Notes for examples.

Figure 7. 80C51 Memory Modes – Separate Space Mode

DPLD

RS0

CSBOOT0-3

FS0-7

PSEN

RD

MAIN

FLASH

CS

OE

FLASH

BOOT

BLOCK

CS

OE

Figure 8. 80C51 Memory Mode – Combined Space Mode

SRAM

CS

OE

RD

VM REG BIT 3

VM REG BIT 4

PSEN

VM REG BIT 1

VM REG BIT 2

VM REG BIT 0

DPLD

RS0

CSBOOT0-3

FS0-7

MAIN

FLASH

CS

OE

FLASH

BOOT

BLOCK

CS

OE

SRAM

CS

OE

RD

30

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