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ST72521R6

8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC, FIVE TIMERS, SPI, SCI, I2C, CAN INTERFACE

STMicroelectronics 

ST72521M/R/AR

SYSTEM INTEGRITY MANAGEMENT (Cont’d)

6.4.2.2 Monitoring a Voltage on the EVD pin

This mode is selected by setting the AVDS bit in

the SICSR register.

The AVD circuitry can generate an interrupt when

the AVDIE bit of the SICSR register is set. This in-

terrupt is generated on the rising and falling edges

of the comparator output. This means it is generat-

ed when either one of these two events occur:

– VEVD rises up to VIT+(EVD)

– VEVD falls down to VIT-(EVD)

The EVD function is illustrated in Figure 16.

For more details, refer to the Electrical Character-

istics section.

Figure 16. Using the Voltage Detector to Monitor the EVD pin (AVDS bit=1)

VEVD

VIT+(EVD)

VIT-(EVD)

Vhyst

AVDF

0

AVD INTERRUPT

REQUEST

IF AVDIE = 1

1

INTERRUPT PROCESS

0

INTERRUPT PROCESS

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