PC85232-1 Ver la hoja de datos (PDF) - NXP Semiconductors.
Número de pieza
componentes Descripción
fabricante
PC85232-1 Datasheet PDF : 54 Pages
| |||
NXP Semiconductors
PCF85132
LCD driver for low multiplex rates
VDD
R
≤
tr
2CB
HOST
MICRO-
PROCESSOR/
MICRO-
CONTROLLER
SDAACK
SDA
SCL
OSC
VDD VLCD
160 segment drives
PCF85132
4 backplanes
LCD PANEL
(up to 640
elements)
VSS
A0 A1 SA0 VSS
013aaa362
Fig 4. Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCF85132.
Biasing voltages for the multiplexed LCD waveforms are generated internally, removing
the need for an external bias generator. The internal oscillator is selected by connecting
pin OSC to VSS. The only other connections required to complete the system are the
power supplies (VDD, VSS, and VLCD) and the LCD panel selected for the application.
7.1 Power-On Reset (POR)
At power-on the PCF85132 resets to the following starting conditions:
• All backplane and segment outputs are set to VLCD
• The selected drive mode is 1:4 multiplex with 1⁄3 bias
• Blinking is switched off
• Input and output bank selectors are reset
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared (set to logic 0)
• The display is disabled
• If internal oscillator is selected (pin OSC connected to VSS), then there is no clock
signal on pin CLK
Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow
the reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider of the three
series resistors connected between VLCD and VSS. The center resistor is bypassed by
switch if the 1⁄2 bias voltage level for the 1:2 multiplex configuration is selected.
PCF85132
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 23 November 2010
© NXP B.V. 2010. All rights reserved.
7 of 54
Share Link: 