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PCA9501D

8-bit I2C and SMBus I/O port with interrupt, 2-kbit EEPROM and 6 address pins

Philips Electronics 

Philips Semiconductors

8-bit I2C and SMBus I/O port with interrupt,

2-kbit EEPROM and 6 address pins

Product data

PCA9501

Acknowledge (see Figure 19)

The number of data bytes transferred between the start and the stop

conditions from transmitter to receiver is not limited. Each byte of

eight bits is followed by one acknowledge bit. The acknowledge bit

is a HIGH level put on the bus by the transmitter whereas the

master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge

after the reception of each byte. Also a master must generate an

acknowledge after the reception of each byte that has been clocked

out of the slave transmitter. The device that acknowledges has to

pull down the SDA line during the acknowledge clock pulse, so that

the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse, set-up and hold times must be

taken into account.

A master receiver must signal an end of data to the transmitter by

not generating an acknowledge on the last byte that has been

clocked out of the slave. In this event the transmitter must leave the

data line HIGH to enable the master to generate a stop condition.

DATA OUTPUT

BY TRANSMITTER

DATA OUTPUT

BY RECEIVER

NOT ACKNOWLEDGE

ACKNOWLEDGE

SCL FROM

MASTER

1

2

S

START

CONDITION

8

9

CLOCK PULSE FOR

ACKNOWLEDGEMENT

Figure 19. Acknowledgment on the I2C-bus

SW00545

2003 Sep 12

12

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