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P83C652EBPN Datasheet PDF : 22 Pages
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Phlips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C652/83C652
AC ELECTRICAL CHARACTERISTICS – I2C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
SCL TIMING CHARACTERISTICS
tHD;STA
START condition hold time
tLOW
SCL LOW time
tHIGH
SCL HIGH time
tRC
SCL rise time
tFC
SCL fall time
SDA TIMING CHARACTERISTICS
≥ 14 tCLCL
≥ 16 tCLCL
≥ 14 tCLCL
≤ 1µs
≤ 0.3µs
> 4.0µs1
> 4.7µs1
> 4.0µs1
–2
< 0.3µs3
tSU;DAT1
Data set-up time
≥ 250ns
> 20 tCLCL – tRD
tSU;DAT2 SDA set-up time (before rep. START cond.)
≥ 250ns
> 1µs1
tSU;DAT3 SDA set-up time (before STOP cond.)
≥ 250ns
> 8 tCLCL
tHD;DAT
Data hold time
≥ 0ns
> 8 tCLCL – tFC
tSU;STA
Repeated START set-up time
≥ 14 tCLCL
> 4.7µs1
tSU;STO
STOP condition set-up time
≥ 14 tCLCL
> 4.0µs1
tBUF
Bus free time
≥ 14 tCLCL
> 4.7µs1
tRD
SDA rise time
≤ 1µs
–2
tFD
SDA fall time
≤ 0.3µs
< 0.3µs3
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 tCLCL will be filtered out. Maximum capacitance on bus-lines SDA and
SCL = 400pF.
4. tCLCL = 1/fOSC = one oscillator clock period at pin XTAL1. For 63ns (42ns) < tCLCL < 285ns (16MHz (24MHz) > fOSC > 3.5MHz) the SI01
interface meets the I2C-bus specification for bit-rates up to 100 kbit/s.
TIMING SIO1 (I2C) INTERFACE
START or repeated START condition
tRD
SDA
(INPUT/OUTPUT)
tFD
tRC
tFC
SCL
(INPUT/OUTPUT)
tHD;STA tLOW
tHIGH
tSU;DAT1
tHD;DAT
repeated START condition
STOP condition
tSU;STA
START condition
tBUF
tSU; STO
0.7 VDD
0.3 VDD
tSU;DAT3
tSU;DAT2
0.7 VDD
0.3 VDD
1997 Dec 05
14
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