AD7533KRZ-REEL Ver la hoja de datos (PDF) - Analog Devices
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AD7533KRZ-REEL Datasheet PDF : 13 Pages
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CIRCUIT DESCRIPTION
GENERAL CIRCUIT INFORMATION
The AD7533 is a 10-bit multiplying DAC that consists of a
highly stable thin-film R-2R ladder and ten CMOS current
switches on a monolithic chip. Most applications require the
addition of only an output operational amplifier and a voltage
or current reference.
The simplified D/A circuit is shown in Figure 7. An inverted
R- 2R ladder structure is used, that is, the binarily weighted
currents are switched between the IOUT1 and IOUT2 bus lines,
thus maintaining a constant current in each ladder leg
independent of the switch state.
VREF
10kΩ
10kΩ
10kΩ
20kΩ
20kΩ
20kΩ
20kΩ
20kΩ
S1
S2
S3
SN
IOUT2
10kΩ
IOUT1
RFB
BIT 1 (MSB)
BIT 2
BIT 3
BIT 10 (LSB)
DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE)
Figure 7. Functional Diagram
One of the CMOS current switches is shown in Figure 8. The
geometries of Device 1, Device 2, and Device 3 are optimized to
make the digital control inputs DTL/TTL/CMOS compatible
over the full military temperature range. The input stage drives
two inverters (Device 4, Device 5, Device 6, and Device 7),
which in turn drive the two output N channels. The on
resistances of the switches are binarily sealed so that the voltage
drop across each switch is the same. For example, Switch 1 in
Figure 8 is designed for an on resistance of 20 Ω, Switch 2 for
40 Ω, and so on. For a 10 V reference input, the current through
Switch 1 is 0.5 mA, the current through Switch 2 is 0.25 mA,
and so on, thus maintaining a constant 10 mV drop across each
switch. It is essential that each switch voltage drop be equal if
the binarily weighted current division property of the ladder is
to be maintained.
AD7533
V+
1
3
DTL/TTL/ 250Ω
CMOS
INPUT
2
4
6
TO LADDER
89
5
7
Figure 8. CMOS Switch
IOUT2 IOUT1
EQUIVALENT CIRCUIT ANALYSIS
The equivalent circuits for all digital inputs high and digital
inputs low are shown in Figure 9 and Figure 10. In Figure 9 with
all digital inputs low, the reference current is switched to IOUT2.
The current source ILEAKAGE is composed of surface and junction
leakages to the substrate, while the I/1024 current source represents
a constant 1-bit current drain through the termination resistor
on the R-2R ladder. The on capacitance of the output N channel
switch is 100 pF, as shown on the IOUT2 terminal. The off switch
capacitance is 35 pF, as shown on the IOUT1 terminal. Analysis of
the circuit for all digital inputs high, as shown in Figure 10, is
similar to Figure 9; however, the on switches are now on
Terminal IOUT1. Therefore, there is the 100 pF at that terminal.
R 10kΩ
IREF
VREF
R
I/1024
R
ILEAKAGE
35pF
ILEAKAGE
100pF
RFB
IOUT1
IOUT2
Figure 9. Equivalent Circuit—All Digital Inputs Low
IREF
VREF
R
R 10kΩ
R
I/1024
ILEAKAGE
100pF
RFB
IOUT1
ILEAKAGE
35pF
IOUT2
Figure 10. Equivalent Circuit—All Digital Inputs High
Rev. C | Page 7 of 12
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