NB6L239 Ver la hoja de datos (PDF) - ON Semiconductor
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NB6L239 Datasheet PDF : 13 Pages
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NB6L239
Table 7. DC CHARACTERISTICS, LVTTL/LVCMOS INPUTS (VCC = 2.375 V to 3.465 V, VEE = 0 V, TA = −40°C to +85°C)
Symbol
Characteristic
Min
Typ
Max
Unit
VIH
Input HIGH Voltage (LVCMOS/LVTTL)
2.0
VCC
V
VIL
Input LOW Voltage (LVCMOS/LVTTL)
VEE
0.8
V
IIH
Input HIGH Current
−150
150
mA
IIL
Input LOW Current
−150
150
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
Table 8. AC CHARACTERISTICS VCC = 2.375 V to 3.465 V; VEE = 0 V (Note 8)
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
finMAX Maximum Input CLOCK Frequency
3.0
3.0
3.0
GHz
VOUTPP Output Voltage Amplitude (Notes 10, 11)
mV
QA(B2, 4, 8), QB(Bn)
fin v 3.0 GHz 450 650
450 650
450 650
QA(B1), QB(Bn)
fin v 2.5 GHz 450 650
450 630
450 610
QA(B1), QB(Bn)
2.5 GHz < fin v 3.0 GHz 300 650
250 650
200 650
tPLH,
tPHL
Propagation Delay to
Output Differential @ 50 MHz
CLK, Qn 370 470 570 370 470 570 400 500 600 ps
MR, Qn 330 370 430 330 380 430 330 400 480
tRR
Reset Recovery
0 −90
0 −90
0 −90
ps
ts
Setup Time @ 50 MHz
EN, CLK 0 −60
SELA/B, CLK 0 −300
0 −60
0 −300
0 −60
ps
0 −300
th
Hold Time @ 50 MHz
CLK, EN 150 65
150 65
150 65
ps
CLK, SELA/B 700 200
700 200
700 200
tskew
Within−Device Skew @ 50 MHz
Device−to−Device Skew
Duty Cycle Skew
(Note 9)
(Note 9)
(Note 9)
5 30
25 80
25 40
5 30
30 90
30 45
6 35 ps
30 90
30 45
tPW
Minimum Pulse Width
MR 550
550
550
ps
tJITTER RMS Random Clock Jitter
(See Figure 20. Fmax/JITTER)
<1
<1
< 1 ps
VINPP Input Voltage Swing (Differential Configuration)
100
(Note 10)
VCC 100
−VEE
VCC 100
−VEE
VCC mV
−VEE
tr
Output Rise/Fall Times @ 50 MHz
Qn, Qn 30 60 120 30 65 120 30 70 120 ps
tf
(20% − 80%)
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification
limit values are applied individually under normal operating conditions and not valid simultaneously.
8. Measured using a 750 mV, 50% duty cycle clock source. All loading with 50 W to VCC − 2.0 V.
9. Skew is measured between outputs under identical transitions and conditions. Duty cycle skew is defined only for differential operation
when the delays are measured from the cross point of the inputs to the cross point of the outputs.
10. Input and output voltage swing is a single−ended measurement operating in differential mode.
11. Output Voltage Amplitude (VOHCLK − VOLCLK) at input CLOCK frequency, fin. The output frequency, fout, is the input CLOCK frequency
divided by n, fout = fin B n. Input CLOCK frequency is v3.0 GHz.
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