NB6L239 Ver la hoja de datos (PDF) - ON Semiconductor

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NB6L239

2.5V / 3.3V Any Differential Clock IN to Differential LVPECL OUT ÷1/2/4/8, ÷2/4/8/16 Clock Divider

ON Semiconductor 

NB6L239

Table 1. PIN DESCRIPTION

Pin

Name

I/O

1

VT

2

CLK

LVPECL, CML, LVDS,

HSTL Input

3

CLK

LVPECL, CML, LVDS,

HSTL Input

4

VBBAC

5

EN*

LVCMOS/LVTTL Input

6

SELB0* LVCMOS/LVTTL Input

7

SELB1* LVCMOS/LVTTL Input

8

VEE

9

QB

Power Supply

LVPECL Output

10

QB

LVPECL Output

11

QA

LVPECL Output

12

QA

LVPECL Output

13

VCC

Power Supply

14 SELA1* LVCMOS/LVTTL Input

15 SELA0* LVCMOS/LVTTL Input

16

MR**

LVCMOS/LVTTL Input

EP

Power Supply (OPT)

*Pins will default LOW when left OPEN.

**Pins will default HIGH when left OPEN.

Description

Internal 100 W Center−Tapped Termination Pin for CLK and CLK.

Noninverted Differential CLOCK Input.

Inverted Differential CLOCK Input.

Output Voltage Reference for Capacitor Coupled Inputs, Only.

Synchronous Output Enable

Clock Divide Select Pin

Clock Divide Select Pin

Negative Supply Voltage

Inverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V.

Noninverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V.

Inverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V.

Noninverted Differential Output. Typically terminated with 50 W resistor to VCC − 2.0 V.

Positive Supply Voltage.

Clock Divide Select Pin

Clock Divide Select Pin

Master Reset Asynchronous, Default Open High, Asserted LOW

The Exposed Pad on the QFN−16 package bottom is thermally connected to the die for

improved heat transfer out of package. The pad is not electrically connected to the die,

but is recommended to be electrically and thermally connected to VEE on the PC board.

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