MX98741 Ver la hoja de datos (PDF) - Macronix International
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fabricante
MX98741 Datasheet PDF : 34 Pages
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MX98741
PAD #
72
73
75
66-70
84-86
78-81, 83
76
74
204
203
Name
JAMO
JAMI
EDATENL
EDAT[0:4]
ACTP[5:8]
ACTP[0:4]
/XRCADD[0:4]
ANYACT
EXTCRS
RESETL
SCRCTRL
B. Expansion Port, 18 pins
I/O
Description
O, TTL Forced Jam Out. Active High. The OR’d forced jam signals ex-
clude JAMI input) controlled by Carrier Integrity Monitor of each
port. If collision occurs inside the XRC, this pin is also asserted.
I, Schm Forced Jam Input. Active High. Asserted by external arbiter, and
XRC will generate JAM patterns to all its ports.
Note : Glitch on JAMI and EDATENL may cause internal state
machine malfunction.
I, Schm Enable Expansion Data. Active Low. Asserted by an external arbitor.
XRC will drive data into EDAT.
I/O, EXP Expansion Data. Bidirectional 5-bit wide data. By default, EDAT is
an input. When EDATENL is low, EDAT changed from input mode
to output mode. Internally pull-up.
O, TTL Activity Out. This is the activity of port 5..8 synchronous to COCLK
(50M clock used by core). It also serves as data framing signal for
the packet on EDAT. ACTP leads EDAT's /J/K/ pattern by more
than 80 ns and deasserted 40ns after the /T/R/ or the last byte of
jam patterns.
I/O, TTL Activity Out/Physical Address. When RESETL goes high, value
on ACTP[0;4] will be latched into internal buffer as physical
address of XRC. After reset, these five pins have the same
function as ACTP[5:8].
O, TTL Any Activity. Active High. The OR’d ACTP[7:0] and TXEN A to C.
This is used as an indication that an XRC is ready to drive data into
EDAT.
I, Schm External Carrier Sense. Active high. Asserted by an external arbitor
indicating activity from other XRC's at the expansion port.
C. Miscellaneous Pins, 2 pins
I, Schm Reset. Active Low. This signal is output by the system to reset all
the logic on the chip.
I, TTL Scrambler Control. If high, the scrambler/descrambler of each port
is individually controlled by MII register 17. If low, the scrambler/
descrambler is bypassed in all the ports.
P/N:PM0342
REV. 1.4, NOV. 07, 1996
4
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