¡ Semiconductor
MSM7653
Timing of Input Data to HSYNC_L
CLKX2
CLKX1O
HSYNC_L
OLR,OLG, OLB, OLC
YD
Invalid Data
Invalid Data
tSTART
Invalid Data
Valid Data
Invalid Data
Cb0 Y00 Cr0 Y01 Cb1 Y10
tACT
Input Timing when BLANK_L is Input
CLKX2
BLANK_L
YD
Cb0 Y00 Cr0 Y01 Cb1
Input timing at 27 MHz in YCbCr format
Timing of Input Data to HSYNC_L
CLKX2
CLKX1O
HSYNC_L
OLR,OLG, OLB, OLC
YD
CD
Invalid Data
Invalid Data
Invalid Data
tSTART
Invalid Data
Invalid Data
Y0
Invalid Data
Cb0
Input Timing when BLANK_L is Input
Y1
Cr0
tACT
Valid Data
Y2
Cb1
CLKX2
BLANK_L
YD
CD
Y0
Y1
Y2
Cb0
Cr0
Cb1
Input timing at 13.5 MHz in YCbCr format
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