MSM514262 Ver la hoja de datos (PDF) - Oki Electric Industry

Número de pieza

componentes Descripción

fabricante

MSM514262

262,144-Word x 4-Bit Multiport DRAM

Oki Electric Industry 

¡ Semiconductor

MSM514262

Read Transfer Operation

Read transfer consists of loading a selected row of data from the RAM into the SAM register.

A read transfer is invoked by holding CAS “high”, DT/OE “low”, WB/WE “high” and DSF

“low” at the falling edge of RAS. The row address selected at the falling edge of RAS determines

the RAM row to be transferred into the SAM. The transfer cycle is completed at the rising edge

of DT/OE. When the transfer is completed, the SAM port is set into the output mode. In a read/

real time read transfer cycle, the transfer of a new row of data is completed at the rising edge

of DT/OE and this data becomes valid on the SIO lines after the specified access time tSCA from

the rising edge of the subsequent SC cycles. The start address of the serial pointer of the SAM

is determined by the column address selected at the falling edge of CAS. In a read transfer cycle

(which is preceded by a write transfer cycle), SC clock must be held at a constant VIL or VIH, after

the SC high time has been satisfied. A rising edge of the SC clock must not occur until after the

specified delay tTSD from the rising edge of DT/OE.

In a real time read transfer cycle (which is preceded by another read transfer cycle), the previous

row data appears on the SIO lines until the DT/OE signal goes “high” and the serial access time

tSCA from the following serial clock is satisfied. This feature allows for the first bit of the new

row of data to appear on the serial output as soon as the last bit of the previous row has been

strobed without any timing loss. To make this continuous data flow possible, the rising edge

of DT/OE must be synchronized with RAS, CAS and the subsequent rising edge of SC (tRTH,

tCTH and tTSL/tTSD must be satisfied).

Write Transfer Operation

Write transfer cycle consists of loading the content of the SAM register into a selected row of the

RAM. If the SAM data to be transferred must first be loaded through the SAM, a pseudo write

transfer operation must precede the write transfer cycles. A write transfer is invoked by holding

CAS “high”, DT/OE “low”, WB/WE “low”, SE “low” at the falling edge of RAS. This write

transfer is selectively controlled per RAM I/O block by setting the mask data on the Wi/IOi

lines at the falling edge of RAS. The row address selected at the falling edge of RAS determines

the RAM row address into which the data will be transferred. The column address selected at

the falling edge of CAS determines the start address of the serial pointer of the SAM. After the

write transfer is completed, the SIO lines are set in the input mode so that serial data

synchronized with the SC clock can be loaded. When consecutive write transfer operation are

performed, new data must not be written into the serial register until the RAS cycle of the

preceding write transfer is completed. Consequently, the SC clock must be held at a constant

VIL or VIH during the RAS cycle. A rising edge of the SC clock is only allowed after the specified

delay tSRD from rising edge of the RAS, at which time a new row of data can be written in the

serial register.

Data transferred to SAM by read transfer cycle or split read transfer cycle can be written to other

address of RAM by write transfer cycle, however, the address to write data must be the same

as that of the read transfer cycle or the split read transfer cycle (row address AX8).

41/45

Share Link: