MPC9658 Ver la hoja de datos (PDF) - Motorola => Freescale
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MPC9658 Datasheet PDF : 12 Pages
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MPC9658
Freescale Semiconductor, Inc.
versus Dual Transmission Lines” illustrates an output driving
a single series terminated line versus two series terminated
lines in parallel. When taken to its extreme the fanout of the
MPC9658 clock driver is effectively doubled due to its
capability to drive multiple lines.
MPC9658
OUTPUT
BUFFER
IN
14Ω
RS = 36Ω ZO = 50Ω
OutA
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
OutA
2.5
tD = 3.8956
OutB
tD = 3.9386
2.0
In
1.5
MPC9658
OUTPUT
BUFFER
IN
14Ω
RS = 36Ω ZO = 50Ω
RS = 36Ω ZO = 50Ω
OutB0
OutB1
Figure 6. Single versus Dual Transmission Lines
The waveform plots in Figure 7. “Single versus Dual Line
Termination Waveforms” show the simulation results of an
output driving a single line versus two lines. In both cases the
drive capability of the MPC9658 output buffer is more than
sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC9658. The output waveform in Figure 7. “Single
versus Dual Line Termination Waveforms” shows a step in
the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 14Ω
VL = 3.0 ( 25 ÷ (18+14+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
1.0
0.5
0
2
4
6
8
10 12 14
TIME (nS)
Figure 7. Single versus Dual Waveforms
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 8. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
MPC9658
OUTPUT
BUFFER
RS = 22Ω ZO = 50Ω
14Ω
RS = 22Ω ZO = 50Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 8. Optimized Dual Line Termination
Differential
W Pulse Generator
Z = 50
ZO = 50 Ω
MPC9658 DUT
ZO = 50 Ω
RT = 50 Ω
VTT
Figure 9. PCLK MPC9658 AC test reference
RT = 50 Ω
VTT
MOTOROLA
For More Informa8tion On This Product,
Go to: www.freescale.com
TIMING SOLUTIONS
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