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GLT4160L04-50TC

4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

G-Link Technology  

G-LINK

GLT4160L04

4M X 4 CMOS DYNAMIC RAM WITH EXTENDED DATA OUTPUT

Nov 2001 (Rev.3.2)

TEST MODE IN CYCLE

RAS VIH-

VIL-

CAS

VIH-

VIL-

WE

VIH-

VIL-

DQ

VI/OH-

VI/OL-

tRP

tRPC

tCP tCSR

tWTS tWTH

tCEZ

tCHR

tRC

tRAS

OPEN

tRP

tRPC

Don't Care

Test Mode

By using the test mode, the test time can be reduced. The reason for this is that, the memory emulates the x

16-bit organization during test mode. Don’t care about the input levels of the CAS input A0, A1 .

(1) Setting the mode

Executing the test mode cycle (WE , CAS before RAS refresh cycle ) sets the test mode.

(2) Write / read operation

When either a “0” or a “1” is written to the input pin in test mode, this data is written to 16 bits of memory

cell.

Next, when the data is read from the output pin at the same address, the cell be checked.

Output = “1” Normal write (all memory cells)

Output = “0” Abnormal write

(3) Refresh

Refresh in the test mode must be performed with the RAS / CAS cycle or with the WE, CAS before RAS

refresh cycle. The WE, CAS before RAS refresh cycle use the same counter as the CAS before RAS

refresh’s internal counter.

(4) Mode Cancellation

The test mode is cancelled by executing one cycle of RAS only refresh cycle or CAS before RAS refresh

cycle.

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