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MH16S64AMA-12

1073741824-BIT (16777216 - WORD BY 64-BIT) SynchronousDRAM

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH16S64AMA -8,-10,-12

1073741824-BIT (16777216 - WORD BY 64-BIT)SynchronousDRAM

[ Read Interrupted by Precharge ]

Burst read operation can be interrupted by precharge of the same or the other bank. Read

to PRE interval is minimum 1 CK. A PRE command disables the data output, depending on

the /CAS Latency. The figure below shows examples, when the dataout is terminated.

Read Interrupted by Precharge (BL=4)

CK

CL=3

Command

DQ

Command

DQ

READ

READ

PRE

Q0 Q1 Q2 Q3

PRE

Q0 Q1

CL=2

Command

DQ

Command

DQ

READ

READ

PRE

Q0 Q1 Q2 Q3

PRE

Q0 Q1

CL=

1

MIT-DS-0127-0.0

Comman

d

DQ

Comman

d

DQ

REA

D

PRE

QQQQ

0

1

2

3

REA

PR

D

E

QQ

0

1

MITSUBISHI

ELECTRIC

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4. Mar.1997

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