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MC44603P

Enhanced Mixed Frequency Mode GreenLine™ PWM Controller:

ON Semiconductor 

MC44603A

Vout

VO

Nominal

Ipk max

VCC

Vdisable2

New Startup

Sequence Initiated

Iout

Overload

Figure 46. Foldback Characteristic

NOTE: Foldback is disabled by connecting Pin 5 to VCC.

Overvoltage Protection

The overvoltage arrangement consists of a comparator

that compares the Pin 6 voltage to Vref (2.5 V) (refer to

Figure 47).

If no external component is connected to Pin 6, the

comparator noninverting input voltage is nearly equal to:

ǒ Ǔ 2.0 kW

11.6 kW ) 2.0 kW

x VCC

The comparator output is high when:

ǒ Ǔ 2.0 kW

11.6 kW ) 2.0 kW

x VCC w 2.5 V

à VCC w 17 V

A delay latch (2.0 ms) is incorporated in order to sense

overvoltages that last at least 2.0 ms.

If this condition is achieved, VOVP out, the delay latch

output, becomes high. As this level is brought back to the

input through an OR gate, VOVP out remains high (disabling

the IC output) until Vref is disabled.

Consequently, when an overvoltage longer than 2.0 ms is

detected, the output is disabled until VCC is removed and

then re−applied.

The VCC is connected after Vref has reached steady state

in order to limit the circuit startup consumption.

The overvoltage section is enabled 5.0 ms after the

regulator has started to allow the reference Vref to stabilize.

By connecting an external resistor to Pin 6, the threshold

VCC level can be changed.

Vref

VCC

Out

T

Delay τ 5.0 ms

0 2.5 V

In

VOVP

External 6

Resistor

11.6 k Enable

2.0 k COVLO

2.5 V

(Vref)

In τ Out

Delay

VOVP out

2.0 ms

(If VOVP out = 1.0,

the Output is Disabled)

Figure 47. Overvoltage Protection

Undervoltage Lockout Section

RF Stby

Rref

Vref enable

Pin 15

Pin 16

VCC

Cstartup

1

10

Reference Block:

Voltage and Current

1

0

Sources Generator

(Vref, Iref, ...)

Vdisable2

7.5 V

Startup

14.5 V

CUVLO1

Vdisable1

9.0 V

UVLO1

(to Soft−Start)

Figure 48. VCC Management

As depicted in Figure 48, an undervoltage lockout has

been incorporated to guarantee that the IC is fully functional

before allowing system operation.

This block particularly, produces Vref (Pin 16 voltage) and

Iref that is determined by the resistor Rref connected between

Pin 16 and the ground:

Iref

+

Vref

Rref

where Vref

+

2.5 V (typically)

Another resistor is connected to the Reference Block:

RF Stby that is used to fix the standby frequency.

In addition to this, VCC is compared to a second threshold

level that is nearly equal to 9.0 V (Vdisable1). UVLO1 is

generated to reset the maximum duty cycle and soft−start

block disabling the output stage as soon as VCC becomes

lower than Vdisable1. In this way, the circuit is reset and made

ready for the next startup, before the reference block is

disabled (refer to Figure 30). Finally, the upper limit for the

minimum normal operating voltage is 9.4 V (maximum

value of Vdisable1) and so the minimum hysteresis is 4.2 V.

((Vstup−th) min = 13.6 V).

The large hysteresis and the low startup current of the

MC44603A make it ideally suited for off−line converter

applications where efficient bootstrap startup techniques are

required.

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