MC14538BDW Ver la hoja de datos (PDF) - Motorola => Freescale
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MC14538BDW Datasheet PDF : 10 Pages
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RETRIGGER OPERATION
The MC14538B is retriggered if a valid trigger occurs fol-
lowed by another valid trigger before the Q output has
returned to the quiescent (zero) state. Any retrigger, after the
timing node voltage at pin 2 or 14 has begun to rise from
Vref 1, but has not yet reached Vref 2, will cause an increase
in output pulse width T. When a valid retrigger is initiated ,
the voltage at CX/RX will again drop to Vref 1 before
progressing along the RC charging curve toward VDD. The Q
output will remain high until time T, after the last valid retrig-
ger.
RESET OPERATION
The MC14538B may be reset during the generation of the
output pulse. In the reset mode of operation, an input pulse
on Reset sets the reset latch and causes the capacitor to be
fast charged to VDD by turning on transistor P1 . When the
voltage on the capacitor reaches Vref 2, the reset latch will
clear, and will then be ready to accept another pulse. It the
Reset input is held low, any trigger inputs that occur will be
inhibited and the Q and Q outputs of the output latch will not
change. Since the Q output is reset when an input low level is
detected on the Reset input, the output pulse T can be made
significantly shorter than the minimum pulse width specifi-
cation.
POWER–DOWN CONSIDERATIONS
Large capacitance values can cause problems due to the
large amount of energy stored. When a system containing
the MC14538B is powered down, the capacitor voltage may
discharge from VDD through the standard protection diodes
at pin 2 or 14. Current through the protection diodes should
be limited to 10 mA and therefore the discharge time of the
VDD supply must not be faster than (VDD). (C)/ (10 mA). For
example, if VDD = 10 V and CX = 10 µF, the VDD supply
should discharge no faster than (10 V) x (10 µF) / (10 mA) =
10 ms. This is normally not a problem since power supplies
are heavily filtered and cannot discharge at this rate.
When a more rapid decrease of VDD to zero volts occurs,
the MC14538B can sustain damage. To avoid this possibility
use an external clamping diode, DX, connected as shown in
Fig. 11.
Cx
VSS
Dx
Rx VDD
VDD
Q
Q
RESET
Figure 11. Use of a Diode to Limit
Power Down Current Surge
PIN ASSIGNMENT
VSS 1
CX/RXA 2
RESET A 3
AA 4
BA 5
QA 6
QA 7
VSS 8
16 VDD
15 VSS
14 CX/RXB
13 RESET B
12 AB
11 BB
10 QB
9 QB
MOTOROLA CMOS LOGIC DATA
MC14538B
7
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