MC100LVEL59 Ver la hoja de datos (PDF) - ON Semiconductor
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MC100LVEL59 Datasheet PDF : 6 Pages
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MC100LVEL59
VCC Q0
20 19
Q0 VCC Q1
18 17 16
Q1 VCC Q2
15 14 13
Q2 VEE
12 11
1
0
1
0
1
0
12345678
COM_SEL D0a D0b SEL0 D1a D1b SEL1 D2a
9 10
D2b SEL2
Warning: All VCC and VEE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20−Lead SOIC (Top View)
Table 1. PIN DESCRIPTION
Pins
Function
D0a−D2a
D0b−D2b
SEL0−SEL2
COM_SEL
Q0−Q2; Q0−Q2
VCC
VEE
ECL Input Data a
ECL Input Data b
ECL Individual Select Input
ECL Common Select Input
ECL Differential Outputs
Positive Supply
Negative Supply
Table 2. TRUTH TABLE
SEL
H
L
Data
a
b
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE
NECL Mode Power Supply
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
Iout
Output Current
VEE = 0 V
VCC = 0 V
VEE = 0 V
VCC = 0 V
Continuous
Surge
VI VCC
VI VEE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
V
50
mA
100
mA
TA
Operating Temperature Range
Tstg
Storage Temperature Range
qJA
Thermal Resistance (Junction to Ambient) 0 lfpm
500 lfpm
20 SOIC
20 SOIC
−40 to +85
−65 to +150
140
100
°C
°C
°C/W
°C/W
qJC
Thermal Resistance (Junction to Case)
Standard Board
20 SOIC
30 to 35
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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