MB91F127/F128
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes
Reset
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Reserved by system
Undefined instruction exception
NMI request
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
UART 0 reception complete
UART 1 reception complete
UART 2 reception complete
UART 0 transmission complete
UART 1 transmission complete
UART 2 transmission complete
Interrupt number
Interrupt level
Decimal Hexadecimal Register*1 Offset
0
00
3FCH
1
01
3F8H
2
02
3F4H
3
03
3F0H
4
04
3ECH
5
05
3E8H
6
06
3E4H
7
07
3E0H
8
08
3DCH
9
09
3D8H
10
0A
3D4H
11
0B
3D0H
12
0C
3CCH
13
0D
3C8H
14
0E
3C4H
15
0F
15 (FH)
fixed
3C0H
16
10
ICR00
3BCH
17
11
ICR01
3B8H
18
12
ICR02
3B4H
19
13
ICR03
3B0H
20
14
ICR04
3ACH
21
15
ICR05
3A8H
22
16
ICR06
3A4H
23
17
ICR07
3A0H
24
18
ICR08
39CH
25
19
ICR09
398H
TBR default
Address*2
000FFFFCH
000FFFF8H
000FFFF4H
000FFFF0H
000FFFECH
000FFFE8H
000FFFE4H
000FFFE0H
000FFFDCH
000FFFD8H
000FFFD4H
000FFFD0H
000FFFCCH
000FFFC8H
000FFFC4H
000FFFC0H
000FFFBCH
000FFFB8H
000FFFB4H
000FFFB0H
000FFFACH
000FFFA8H
000FFFA4H
000FFFA0H
000FFF9CH
000FFF98H
(Continued)
22