MB15E05LPV Ver la hoja de datos (PDF) - Fujitsu

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fabricante

MB15E05LPV

Single Serial Input PLL Frequency Synthesizer On-Chip 2.0 GHz Prescaler

Fujitsu 

MB15E05L

Programmable Reference Counter

LSB

Data Flow

MSB

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CA A A A A A A N N N N N N N N N N N

N 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11

T

CNT

: Control bit

N1 to N11 : Divide ratio setting bits for the programmable counter (5 to 2,047)

A1 to A7 : Divide ratio setting bits for the swallow counter (0 to 127)

Note: Start data input with MSB first

[Table. 1]

[Table. 3]

[Table. 4]

Table2. Binary 14-bit Programmable Reference Counter Data Setting (R1 to R14)

Divide

ratio

(R)

RRRRRRRRRRRRRR

14 13 12 11 10 9 8 7 6 5 4 3 2 1

5

00000000000101

6

00000000000110

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

16383

11111111111111

Note: • Divide ratio less than 5 is prohibited.

Table.3 Binary 11-bit Programmable Counter Data Setting (N1 to N11)

Divide

ratio

(N)

NNNNNNNNNNN

11 10 9 8 7 6 5 4 3 2 1

5

00000000101

6

00000000110

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

⋅

2047

11111111111

Note: • Divide ratio less than 5 is prohibited.

• Divide ratio (N) range = 5 to 2,047

8

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