M470L3223DT0-CA0 Ver la hoja de datos (PDF) - Samsung
Número de pieza
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fabricante
M470L3223DT0-CA0 Datasheet PDF : 16 Pages
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M470L3223DT0
AC Timming Parameters & Specifications (These AC charicteristics were tested on the Component)
Parameter
-TCB3(DDR333)
Symbol
Unit
Min
Max
Note
Row cycle time
tRC
60
ns
Refresh row cycle time
tRFC
72
ns
Row active time
tRAS
42
70K ns
RAS to CAS delay
tRCD
18
ns
Row precharge time
tRP
18
ns
Row active to Row active delay
tRRD
12
ns
Write recovery time
tWR
15
ns
Last data in to Read command
tWTR
1
tCK
Clock cycle time
CL=2.0
7.5
tCK
CL=2.5
6
12
ns
4
12
ns
4
Clock high level width
tCH
0.45
0.55 tCK
Clock low level width
tCL
0.45
0.55 tCK
DQS-out access time from CK/CK
tDQSCK -0.6
+0.6 ns
Output data access time from CK/CK
tAC
-0.7
+0.7 ns
Data strobe edge to ouput data edge
tDQSQ
-
0.45 ns
4
Read Preamble
tRPRE 0.9
1.1 tCK
Read Postamble
tRPST 0.4
0.6 tCK
CK to valid DQS-in
tDQSS 0.75
1.25 tCK
DQS-in setup time
tWPRES 0
ns
2
Write Preamble
tWPRE 0.25
tCK
Write Postamble
tWPST 0.4
0.6 tCK
3
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH 0.35
tCK
DQS-in low level width
tDQSL 0.35
tCK
Address and Control Input setup/hold time
(fast slew rate)
tIS/tIH
0.75
ns
Address and Control Input setup/hold time
(slow slew rate)
tIS/tIH
0.8
ns
DQ and DM input setup time
tDS
0.45
ns
DQ and DM input hold time
tDH
0.45
ns
Data-out high impedence time from CK/CK
tHZ
-0.7
+0.7 ps
Data-out low impedence time from CK/CK
tLZ
-0.7
+0.7 ps
Rev. 0.0 Dec. 2001
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