LTC4365CDDBTRMPBF Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

fabricante

LTC4365CDDBTRMPBF

UV, OV and Reverse Supply Protection Controller

Linear Technology 

LTC4365

APPLICATIONS INFORMATION

The trace at VOUT, on the other hand, does not respond

to the negative voltage at VIN, demonstrating the desired

reverse supply protection. The waveforms of Figure 7 were

captured using a 40V dual N-channel MOSFET, a 10μF

ceramic output capacitor and no load current on VOUT.

Recovery Timer

The LTC4365 has a recovery delay timer that filters noise

at VIN and helps prevent chatter at VOUT. After either an OV

or UV fault has occurred, the input supply must return to

the desired operating voltage window for at least 36ms in

order to turn the external MOSFET back on as illustrated

in Figures 4 and 5.

Going out of and then back into fault in less than 36ms

will keep the MOSFET off continuously. Similarly, coming

out of shutdown (SHDN low to high) triggers an 800μs

start-up delay timer (see Figure 10).

The recovery timer is also active while the LTC4365 is

powering up. The 36ms timer starts once VIN rises above

VIN(UVLO) and VIN lies within the user selectable UV/OV

power good window. See Figure 8.

VIN

VIN(UVLO)

tRECOVERY

GATE

MOSFET OFF

MOSFET ON

4365 F08

Figure 8. Recovery Timing During Power-On

(OV = GND, UV = SHDN = VIN)

Gentle Shutdown

The SHDN input turns off the external MOSFETs in a

gentle, controlled manner. When SHDN is asserted low,

a 90μA current sink slowly begins to turn off the external

MOSFETs.

Once the voltage at the GATE pin falls below the voltage

at the VOUT pin, the current sink is throttled back and a

feedback loop takes over. This loop forces the GATE voltage

to track VOUT, thus keeping the external MOSFETs off as

VOUT decays. Note that when VOUT < 4.5V, the GATE pin

is pulled to within 400mV of ground.

Gentle gate turn off reduces load current slew rates and

mitigates voltage spikes due to parasitic inductances.

To further decrease GATE pin slew rate, place a capaci-

tor across the gate and source terminals of the external

MOSFETs. The waveforms of Figure 9 were captured using

the Si4230 dual N-channel MOSFETs, and a 2A load with

100μF output capacitor.

GATE

VOUT

5V/DIV

SHDN

GND

VIN = 12V

T = 25°C

100μs/DIV

4365 F9

Figure 9. Gentle Shutdown: GATE Tracks VOUT as

VOUT Decays

FAULT Status

The FAULT high voltage open drain output is driven low if

SHDN is asserted low, if VIN is outside the desired UV/OV

voltage window, or if VIN has not risen above VIN(UVLO).

Figures 4, 5 and 10 show the FAULT output timing.

SHDN

GATE

VOUT

FAULT

ΔVGATE

tGATE(SLOW)

tSTART

GATE = VOUT

tSHDN(F)

Figure 10. Gentle Shutdown Timing

4365 F10

4365f

12

Share Link: