LTC2602 Ver la hoja de datos (PDF) - Linear Technology

Número de pieza

componentes Descripción

fabricante

LTC2602

Dual 16-/14-/12-Bit Rail-to-Rail DACs in 8-Lead MSOP

Linear Technology 

LTC2602/LTC2612/LTC2622

U

OPERATIO

Power-On Reset

The LTC2602/LTC2612/LTC2622 clear the outputs to zero

scale when power is first applied, making system initializa-

tion consistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2602/

LTC2612/LTC2622 contain circuitry to reduce the power-

on glitch; furthermore, the glitch amplitude can be made

smaller by reducing the ramp rate of the power supply. For

example, if the power supply is ramped to 5V in 1ms, the

analog outputs rise less than 10mV above ground (typ)

during power-on. See Power-On Reset Glitch in the Typi-

cal Performance Characteristics section.

Power Supply Sequencing

The voltage at REF (Pin 4) should be kept within the range

– 0.3V ≤ VREF ≤ VCC + 0.3V (see Absolute Maximum

Ratings). Particular care should be taken to observe these

limits during power supply turn-on and turn-off sequences,

when the voltage at VCC (Pin 6) is in transition.

Transfer Function

The digital-to-analog transfer function is

VOUT(IDEAL)

=

⎛⎝⎜

k

2N

⎞⎠⎟

VREF

where k is the decimal equivalent of the binary DAC input

code, N is the resolution and VREF is the voltage at REF

(Pin 4).

Table 1.

COMMAND*

C3 C2 C1 C0

0 0 0 0 Write to Input Register n

0 0 0 1 Update (Power Up) DAC Register n

0 0 1 0 Write to Input Register n, Update (Power Up) All n

0 0 1 1 Write to and Update (Power Up) n

0 1 0 0 Power Down n

1 1 1 1 No Operation

ADDRESS (n)*

A3 A2 A1 A0

0 0 0 0 DAC A

0 0 0 1 DAC B

1 1 1 1 All DACs

*Command and address codes not shown are reserved and should not be used.

10

Serial Interface

The CS/LD input is level triggered. When this input is taken

low, it acts as a chip-select signal, activating the SDI and

SCK buffers and enabling the input shift register. Data

(SDI input) is transferred at the next 24 rising SCK edges.

The 4-bit command, C3-C0, is loaded first; then the 4-bit

DAC address, A3-A0; and finally the 16-bit data word. The

data word comprises the 16-, 14- or 12-bit input code,

ordered MSB-to-LSB, followed by 0, 2 or 4 don’t-care bits

(LTC2602, LTC2612 and LTC2622 respectively). Data can

only be transferred to the device when the CS/LD signal is

low.The rising edge of CS/LD ends the data transfer and

causes the device to carry out the action specified in the

24-bit input word. The complete sequence is shown in

Figure 2a.

The command (C3-C0) and address (A3-A0) assignments

are shown in Table 1. The first four commands in the table

consist of write and update operations. A write operation

loads a 16-bit data word from the 32-bit shift register into

the input register of the selected DAC, n. An update

operation copies the data word from the input register to

the DAC register. Once copied into the DAC register, the

data word becomes the active 16-, 14- or 12-bit input

code, and is converted to an analog voltage at the DAC

output. The update operation also powers up the selected

DAC if it had been in power-down mode. The data path and

registers are shown in the block diagram.

While the minimum input word is 24 bits, it may optionally

be extended to 32 bits to accommodate microprocessors

which have a minimum word width of 16 bits (2 bytes). To

use the 32-bit word width, 8 don’t-care bits are transferred

to the device first, followed by the 24-bit word as just

described. Figure 2b shows the 32-bit sequence.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever less

than two outputs are needed. When in power-down, the

buffer amplifiers, bias circuits and reference inputs are

disabled, and draw essentially zero current. The DAC

outputs are put into a high-impedance state, and the

2602fa

Share Link: