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LTC2269

16-Bit, 20Msps Low Noise ADC

Linear Technology 

LTC2269

APPLICATIONS INFORMATION

Encode Input

The signal quality of the encode inputs strongly affects the

A/D noise performance. The encode inputs should be treated

as analog signals—do not route them next to digital traces

on the circuit board. There are two modes of operation for

the encode inputs: the differential encode mode (Figure 10),

and the single-ended encode mode (Figure 11).

LTC2269

VDD

VDD

DIFFERENTIAL

COMPARATOR

15k

ENC+

ENC–

30k

2269 F10

Figure 10. Equivalent Encode Input

Circuit for Differential Encode Mode

LTC2269

1.8V TO 3.3V

0V

ENC+

ENC–

30k

CMOS LOGIC

BUFFER

2269 F11

Figure 11. Equivalent Encode Input

Circuit for Single-Ended Encode Mode.

The differential encode mode is recommended for sinu-

soidal, PECL, or LVDS encode inputs (Figures 12, 13).

The encode inputs are internally biased to 1.2V through

10kΩ equivalent resistance. The encode inputs can be

taken above VDD (up to 3.6V), and the common mode

range is from 1.1V to 1.6V. In the differential encode

mode, ENC– should stay at least 200mV above ground to

avoid falsely triggering the single-ended encode mode.

For good jitter performance ENC+ and ENC– should have

fast rise and fall times.

The single ended encode mode should be used with

CMOS encode inputs. To select this mode, ENC– is con-

nected to ground and ENC+ is driven with a square wave

0.1μF

T1

0.1μF

ENC+

LTC2269

50Ω

100Ω

50Ω

T1 = MA/COM ETC1-1-13

RESISTORS AND CAPACITORS

ARE 0402 PACKAGE SIZE

0.1μF ENC–

2269 F12

Figure 12. Sinusoidal Encode Drive

PECL OR

LVDS

CLOCK

0.1μF

ENC+

0.1μF

ENC–

LTC2269

2269 F13

Figure 13. PECL or LVDS Encode Drive

encode input. ENC+ can be taken above VDD (up to 3.6V)

enabling 1.8V to 3.3V CMOS logic levels to be used. The

ENC+ threshold is 0.9V. For good jitter performance ENC+

should have fast rise and fall times.

If the encode signal is turned off or drops below approxi-

mately 500kHz, the A/D enters nap mode.

Clock Duty Cycle Stabilizer

For good performance the encode signal should have a

50%(±5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 10% to 90% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency, the duty cycle stabilizer circuit

requires one hundred clock cycles to lock onto the input

clock. The duty cycle stabilizer is enabled by mode control

register A2 (serial programming mode), or by CS (parallel

programming mode).

For applications where the sample rate needs to be changed

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

to make the sampling clock have a 50%(±5%) duty cycle.

The duty cycle stabilizer should not be used below 2Msps.

2269f

19

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