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LTC2240UP-10

10-Bit, 170Msps ADC

Linear Technology 

LTC2240-10

APPLICATIONS INFORMATION

Input Drive Impedance

As with all high performance, high speed ADCs, the dy-

namic performance of the LTC2240-10 can be influenced

by the input drive circuitry, particularly the second and

third harmonics. Source impedance and input reactance

can influence SFDR. At the falling edge of ENC, the

sample-and-hold circuit will connect the 2pF sampling

capacitor to the input pin and start the sampling period.

The sampling period ends when ENC rises, holding the

sampled input on the sampling capacitor. Ideally the

input circuitry should be fast enough to fully charge the

sampling capacitor during the sampling period 1/(2fS);

however, this is not always possible and the incomplete

settling may degrade the SFDR. The sampling glitch has

been designed to be as linear as possible to minimize the

effects of incomplete settling.

For the best performance, it is recommended to have a

source impedance of 100Ω or less for each input. The

source impedance should be matched for the differential

inputs. Poor matching will result in higher even order

harmonics, especially the second.

Input Drive Circuits

Figure 3 shows the LTC2240-10 being driven by an RF

transformer with a center tapped secondary. The secondary

center tap is DC biased with VCM, setting the ADC input

signal at its optimum DC level. Terminating on the trans-

former secondary is desirable, as this provides a common

mode path for charging glitches caused by the sample and

hold. Figure 3 shows a 1:1 turns ratio transformer. Other

turns ratios can be used if the source impedance seen

by the ADC does not exceed 100Ω for each ADC input.

A disadvantage of using a transformer is the loss of low

frequency response. Most small RF transformers have

poor performance at frequencies below 1MHz.

Figure 4 demonstrates the use of a differential amplifier to

convert a single ended input signal into a differential input

signal. The advantage of this method is that it provides

low frequency input response; however, the limited gain

bandwidth of most op amps will limit the SFDR at high

input frequencies.

Figure 5 shows a capacitively-coupled input circuit. The im-

pedance seen by the analog inputs should be matched.

The 25Ω resistors and 12pF capacitor on the analog inputs

serve two purposes: isolating the drive circuitry from

10Ω

0.1μF T1

ANALOG

1:1

INPUT

25Ω

25Ω 0.1μF

25Ω 25Ω

T1 = MA/COM ETC1-1T

RESISTORS, CAPACITORS

ARE 0402 PACKAGE SIZE

VCM

2.2μF

AIN+

AIN+

12pF

AIN–

AIN–

LTC2240-10

224010 F03

Figure 3. Single-Ended to Differential

Conversion Using a Transformer

50Ω

HIGH SPEED

DIFFERENTIAL

AMPLIFIER 25Ω

ANALOG

INPUT

+

+

3pF

CM

0.1μF – –

25Ω

3pF

VCM

2.2μF

AIN+

AIN+

12pF

AIN–

AIN–

LTC2240-10

224010 F04

Figure 4. Differential Drive with an Amplifier

0.1μF

100Ω 100Ω

25Ω

ANALOG

INPUT

0.1μF

25Ω

VCM

2.2μF

AIN+

LTC2240-10

AIN+

12pF AIN–

AIN–

224010 F05

Figure 5. Capacitively-Coupled Drive

16

224010fb

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