LT3495 Ver la hoja de datos (PDF) - Linear Technology
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LT3495 Datasheet PDF : 16 Pages
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LT3495/LT3495B/
LT3495-1/LT3495B-1
APPLICATIONS INFORMATION
can be set by the value of RCTRL and CCTRL. The following
expression can be used to design the soft-start time:
TSTARTUP
=
RCTRL
•
CCTRL
• In
VSHDVNSH–D1N.235
where VSHDN is the voltage at SHDN pin when the part is
enabled. To ensure soft-start will work, the initial voltage
at CTRL pin when the part is enabled should be close to
0V. The soft-start may not work if this initial condition is
not satisfied.
Output Disconnect
The LT3495 series has an output disconnect PMOS that
blocks the load from the input during shutdown. During
normal operation, the maximum current through the PMOS
is limited by circuitry inside the chip. When the CAP and
VOUT voltage difference is more than 8.7V (typ), the cur-
rent through the PMOS is no longer limited, and can be
much higher. As a result, forcing 8.7V or higher voltage
from the CAP to the VOUT pins can damage the PMOS.
In cases when the CAP voltage is high and/or a large ca-
pacitor is used at the CAP pin, shorting VOUT to GND can
cause large PMOS currents to flow. Under this condition,
the PMOS peak current should be kept at less than 1A.
Also be aware of the thermal dissipation in the PMOS at
all times. In addition, if the input voltage is more than 8V,
the PMOS will turn on during shutdown, resulting in the
output voltage no longer being blocked from the input.
Under this condition, the output voltage will be about 8V
lower than the input voltage.
Board Layout Considerations
As with all switching regulators, careful attention must be
paid to the PCB board layout and component placement.
To maximize efficiency, switch rise and fall times are made
as short as possible. To prevent electromagnetic interfer-
ence (EMI) problems, proper layout of the high frequency
switching path is essential. The voltage signal of the
SW pin has sharp rising and falling edges. Minimize the
length and area of all traces connected to the SW pin and
always use a ground plane under the switching regulator
to minimize interplane coupling. In addition, the FB pin
feeds into the internal error amplifier and is sensitive to
noise. Minimizing the length and area of all traces to this
pin is recommended. Connect the feedback resistor R1
directly from the VOUT pin to the FB pin and keep the trace
as short as possible. Recommended component placement
is shown in Figure 6.
12
GND
SW
GND
CAP
VCC GND CAP
CTRL
SHDN
VOUT
FB
GND
CTRL SHDN
VIAS TO GROUND PLANE REQUIRED
TO IMPROVE THERMAL PERFORMANCE
3495 F06
VIAS FOR CAP GROUND RETURN THROUGH
SECOND METAL LAYER, CAPACITOR GROUNDS
MUST BE RETURNED DIRECTLY TO IC GROUND
Figure 6. Recommended Board Layout
3495b1b1f
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