SAA5284 Ver la hoja de datos (PDF) - Philips Electronics
Número de pieza
componentes Descripción
fabricante
SAA5284 Datasheet PDF : 24 Pages
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Philips Semiconductors
Multimedia video data acquisition circuit
Objective specification
SAA5284
handbook, full pagewidth
DMARQ
DMACK
CS
(same signal
as DMACK)
RD(1)
D7 to D0
t1
t3
t4
t5
t6
t7
valid data
t2
valid data
MGK147
(1) Read data pipelined, so no RD LOW to data valid set-up time.
Fig.5 Intel mode interface DMA cycle timing.
Table 5 Intel-mode interface DMA cycle timing (12 MHz clock)
SYMBOL
t1
t2
t3
t4
t5
t6
t7
DESCRIPTION
DMARQ to DMACK
RD LOW to DMARQ LOW
cycle time
DMACK to RD active
data set-up time
data hold time
data hold from DMACK HIGH
Note
1. This timing will be up to 3 clock cycles for the first read in DMA transfer.
MIN.
0
0
252
−
0
83
0
MAX.
−
212
−
0
90(1)
−
83
UNIT
ns
ns
ns
ns
ns
ns
ns
1998 Feb 05
14
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