
KM68512A Family
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
Address
CS1
CS2
WE
Data in
Data out
tAS(3)
Data Undefined
tWC
tCW(2)
tWR(4)
tAW
tCW(2)
tWP(1)
tWHZ
tDW
tDH
Data Valid
tOW
CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)
Address
CS1
tAS(3)
tWC
tCW(2)
tAW
tWR(4)
CS2
tWP(1)
WE
Data in
tDW
tDH
Data Valid
Data out
High-Z
High-Z
7
Revision 4.0
January 1997