ISL97649B Ver la hoja de datos (PDF) - Intersil
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ISL97649B Datasheet PDF : 19 Pages
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ISL97649B
Layout Recommendations
The device's performance, including efficiency, output noise,
transient response and control loop stability, is dramatically
affected by the PCB layout. PCB layout is critical, especially at
high switching frequency.
Some general guidelines for layout:
1. Place the external power components (the input capacitors,
output capacitors, boost inductor and output diodes, etc.) in
close proximity to the device. Traces to these components
should be kept as short and wide as possible to minimize
parasitic inductance and resistance.
2. Place VDC and VREF bypass capacitors close to the pins.
3. Reduce the loop with large AC amplitudes and fast slew rate.
4. The feedback network should sense the output voltage
directly from the point of load and should be as far away from
the LX node as possible.
5. The power ground (PGND) and signal ground (SGND) pins
should be connected at the ISL97649B exposed die plate
area.
6. The exposed die plate, on the underside of the package,
should be soldered to an equivalent area of metal on the PCB.
This contact area should have multiple via connections to the
back of the PCB as well as connections to intermediate PCB
layers, if available, to maximize thermal dissipation away
from the IC.
7. To minimize thermal resistance of the package when
soldered to a multi-layer PCB, the amount of copper track and
ground plane area connected to the exposed die plate should
be maximized and spread out as far as possible from the IC.
The bottom and top PCB areas especially should be
maximized to allow thermal dissipation to the surrounding air.
8. Minimize feedback input track lengths to avoid switching
noise pick-up.
The ISL97649BIRTZ-EVALZ evaluation board is available to
illustrate the proper layout implementation.
17
FN7927.0
December 5, 2011
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