ISL8025 Ver la hoja de datos (PDF) - Intersil

Número de pieza

componentes Descripción

fabricante

ISL8025

Compact Synchronous Buck Regulators

Intersil 

ISL8025, ISL8025A

PWM

PFM

PWM

CLOCK

16 CYCLES

PFM CURRENT LIMIT

IL

0

NOMINAL +1%

LOAD CURRENT

VOUT

NOMINAL

NOMINAL -1.5%

FIGURE 49. SKIP MODE OPERATION WAVEFORMS

Frequency Adjust

The frequency of operation is fixed at 1MHz when FS is tied to VIN.

Adjustable frequency ranges from 500kHz to 4MHz via a simple

resistor connecting FS to SGND, according to Equation 2:

RFS[kΩ] = -f-O--2---S2---0-C----[⋅---k1---H0----3-z----] – 14

(EQ. 2)

Overcurrent Protection

The overcurrent protection is realized by monitoring the CSA

output with the OCP comparator, as shown in Figure 3. The current

sensing circuit has a gain of 200mV/A, from the P-FET current to

the CSA output. When the CSA output reaches the threshold, the

OCP comparator is trippled to turn off the P-FET immediately. The

overcurrent function protects the switching converter from a

shorted output by monitoring the current flowing through the

upper MOSFET.

Upon detection of an overcurrent condition, the upper MOSFET

will be immediately turned off and will not be turned on again

until the next switching cycle. Upon detection of the initial

overcurrent condition, the overcurrent fault counter is set to 1. If,

on the subsequent cycle, another overcurrent condition is

detected, the OC fault counter will be incremented. If there are

17 sequential OC fault detections, the regulator will be shut down

under an overcurrent fault condition. An overcurrent fault

condition will result in the regulator attempting to restart in a

hiccup mode within the delay of eight soft-start periods. At the

end of the 8th soft-start wait period, the fault counters are reset

and soft-start is attempted again. If the overcurrent condition

goes away during the delay of 8 soft-start periods, the output will

resume back into regulation point after hiccup mode expires.

Negative Current Protection

Similar to overcurrent, the negative current protection is realized

by monitoring the current across the low-side N-FET, as shown in

Figure 3 on page 5. When the valley point of the inductor current

reaches -3A for 4 consecutive cycles, both P-FET and N-FET are off.

The 100Ω in parallel to the N-FET will activate discharging the

output into regulation. The control will begin to switch when output

is within regulation. The regulator will be in PFM for 20µs before

switching to PWM if necessary.

PG

PG is an open-drain output of a window comparator that

continuously monitors the buck regulator output voltage. PG is

actively held low when EN is low and during the buck regulator

soft-start period. After 1ms delay of the soft-start period, PG

becomes high impedance as long as the output voltage is within

nominal regulation voltage set by VFB. When VFB drops 15% below

or raises 0.8V above the nominal regulation voltage, the ISL8025,

ISL8025A pulls PG low. Any fault condition forces PG low until the

fault condition is cleared by attempts to soft-start. For logic level

output voltages, connect an external pull-up resistor, R1, between

PG and VIN. A 100kΩ resistor works well in most applications.

UVLO

When the input voltage is below the undervoltage lock-out (UVLO)

threshold, the regulator is disabled.

Soft Start-Up

The soft-start-up reduces the in-rush current during the start-up.

The soft-start block outputs a ramp reference to the input of the

error amplifier. This voltage ramp limits the inductor current as

well as the output voltage speed, so that the output voltage rises

in a controlled fashion. When VFB is less than 0.1V at the

beginning of the soft-start, the switching frequency is reduced to

200kHz, so that the output can start-up smoothly at light load

condition. During soft-start, the IC operates in the SKIP mode to

support pre-biased output condition.

Tie SS to SGND for internal soft-start is approximately 1ms.

Connect a capacitor from SS to SGND to adjust the soft-start

time. This capacitor, along with an internal 1.85µA current

source sets the soft-start interval of the converter, tSS, as shown

by Equation 3.

CSS[μF] = 3.1 ⋅ tSS[s]

(EQ. 3)

CSS must be less than 33nF to insure proper soft-start reset after

fault condition.

Enable

The enable (EN) input allows the user to control the turning on or

off of the regulator for purposes, such as power-up sequencing.

When the regulator is enabled, there is typically a 600µs delay

17

FN8357.0

February 20, 2013

Share Link: