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SAA7186

Digital video scaler

Philips Electronics 

Philips Semiconductors

Digital video scaler

Preliminary specification

SAA7186

7 FUNCTIONAL DESCRIPTION

The input port is output of Philips digital video

multistandard decoders (SAA7151B, SAA7191B) or other

similar sources.

The SAA7186 input supports the 16-bit YUV 4:2:2 format.

The video data from the input port are converted into a

unique internal two’s complement data stream and are

processed in horizontal direction in two separate

decimation filters. Then they are processed in vertical

direction by the vertical processing unit (VPU).

Chrominance data are interpolated to a 4:4:4 format; a

chroma keying bit is generated.

The 4:4:4 YUV data are then converted from the YUV to

the RGB domain in a digital matrix. ROM tables in the RGB

data path can be used for anti-gamma correction of

gamma-corrected input signals.

Uncorrected RGB and YUV signals can be bypassed.

A scale control unit generates reference and gate signals

for scaling of the processed video data. After data

formatting to the various VRAM port formats, the scaled

video data are buffered in the 16 word × 32-bit output FIFO

register. The FIFO output is directly connected to the

VRAM output bus VRO(31-0). Specific reference signals

support an easy memory interfacing.

All functions of the SAA7186 are controlled via I2C-bus

using 17 subaddresses. The external microcontroller can

get information by reading the status register.

7.1 Video input port

The 16-bit YUV input data in 4:2:2 format (Table 1) consist

of 8-bit luminance data Y (pins YIN(7-0)) and 8-bit

time-multiplexed colour-difference data UV (pins

UVIN(7-0)).

The input data are clocked in by the signals LLC and

CREF (Fig.3). HREF and VS inputs define the video scan

pattern (window).

Sequential input data

• are limited to maximum 768 active pixels per line if the

vertical filter is active

• UV can be processed in straight binary and two’s

complement representation (controlled by TCC)

7.2 Decimation filters

The decimation filters perform accurate horizontal filtering

of the input data stream.

Signal characteristics are matched in front of the pixel

decimation stage, thus disturbing artifacts, caused by the

pixel dropping, are reduced. The signal bandwidth can be

reduced in steps of:

2-tap filter = −6 dB at 0.325 pixel rate

3-tap filter = −6 dB at 0.25 pixel rate

4-tap filter = −6 dB at 0.21 pixel rate

5-tap filter = −6 dB at 0.125 pixel rate

9-tap filter = −6 dB at 0.075 pixel rate

The different characteristics are chosen dependent on the

defined scaling parameters in an adaptive filter mode

(AFS-bit = 1).

The filter characteristics can also be selected

independently by control bits HF2 to HF0 at AFS-bit = 0.

7.3 Vertical filters

Y and UV data are handled in separate filters (Fig.1). Each

of the two line memories has a capacity of 2 × 768 × 8-bit.

Thus two complete video lines of 4:2:2 YUV data can be

stored. The VPU is split into two memory banks and one

arithmetic unit. The available processing modes,

respectively transfer functions, are selectable by the bits

VP1 and VP0 if AFS = 0.

An adaptive mode is selected by AFS = 1. Disturbing

artifacts, generated by line dropping, are reduced.

Adaptive filter selection (AFS = 1):

SCALING RATIO

XD/XS

≤1

≤14/15

≤11/15

≤7/15

≤3/15

YD/YS

≤1

≤13/15

≤4/15

FILTER FUNCTION

(REFER TO I2C SECTION)

horizontal

bypassed

filter 1

filter 6

filter 3

filter 4

vertical

bypassed

filter 1

filter 2

May 1993

9

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