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IDT82V3385EQG
(Rev.:2009)

SYNCHRONOUS ETHERNET WAN PLL

Integrated Device Technology 

IDT82V3385

SYNCHRONOUS ETHERNET WAN PLL

3.3 INPUT CLOCKS & FRAME SYNC SIGNAL

Altogether 5 clocks and 1 frame sync signal are input to the device.

3.3.1 INPUT CLOCKS

The device provides 5 input clock ports.

According to the input port technology, the input ports support the fol-

lowing technologies:

• PECL/LVDS

• CMOS

According to the input clock source, the following clock sources are

supported:

• T1: Recovered clock from STM-N or OC-n

• T2: PDH network synchronization timing

• T3: External synchronization reference timing

IN1, IN2 and IN5 support CMOS input signal only and the clock

sources can be from T1, T2 or T3.

IN3 and IN4 support PECL/LVDS input signal only and automatically

detect whether the signal is PECL or LVDS. The clock sources can be

from T1, T2 or T3.

For SDH and SONET networks, the default frequency is different.

SONET / SDH frequency selection is controlled by the IN_SONET_SDH

bit. During reset, the default value of the IN_SONET_SDH bit is deter-

mined by the SONET/SDH pin: high for SONET and low for SDH. After

reset, the input signal on the SONET/SDH pin takes no effect.

3.3.2 FRAME SYNC INPUT SIGNALS

A 2 kHz, 4 kHz or 8 kHz frame sync signal is input on the EX_SYNC1

pin. It is a CMOS input. The input frequency should match the setting in

the SYNC_FREQ[1:0] bits.

The frame sync input signal is used for frame sync output signal syn-

chronization. Refer to Chapter 3.13.2 Frame SYNC Output Signals for

details.

Table 3: Related Bit / Register in Chapter 3.3

Bit

IN_SONET_SDH

SYNC_FREQ[1:0]

Register

INPUT_MODE_CNFG

Address (Hex)

09

Functional Description

19

March 23, 2009

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