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IDT79R3081E

RISController with FPA

Integrated Device Technology 

IDT79R3081 RISController

MILITARY AND COMMERCIAL TEMPERATURE RANGES

AC ELECTRICAL CHARACTERISTICS RV3081 (cont.)

COMMERCIAL TEMPERATURE RANGE(1, 2)— (TC = 0°C to +85°C, VCC = +3.3V ±5%)

20MHz

25MHz

Symbol Signals

t18 A/D

t19 A/D

Description

Tri-state from SysClk falling

SysClk falling to data valid

Min.

—

—

Max.

10

13

Min.

—

—

Max.

10

12

Unit

ns

ns

t20 ClkIn (2x clock mode)

Pulse Width HIGH

10

—

8

—

ns

t21 ClkIn (2x clock mode)

Pulse Width LOW

10

—

8

—

ns

t22 ClkIn (2x clock mode)

Clock Period

t23 Reset

Pulse Width from Vcc valid

t24 Reset

Minimum Pulse Width

t25 Reset

Set-up to SysClk falling

t26 Int

Mode set-up to Reset rising

t27 Int

Mode hold from Reset rising

t28 SInt, SBrCond

Set-up to SysClk falling

t29 SInt, SBrCond

Hold from SysClk falling

t30 Int, BrCond

Set-up to SysClk falling

t31 Int, BrCond

Hold from SysClk falling

tsys SysClk (full frequency mode) Pulse Width(5)

t32 SysClk (full frequency mode) Clock High Time(5)

25

250

20

250

ns

200

—

200

—

µs

32

—

32

—

tsys

6

—

5

—

ns

10

—

9

—

ns

0

—

0

—

ns

6

—

5

—

ns

3

—

3

—

ns

6

—

5

—

ns

3

—

3

—

ns

2*t22

2*t22

2*t22

2*t22

ns

t22-2

t22+2

t22-2

t22+2

ns

t33

tsys/2

t34

t35

t36

t37

SysClk (full frequency mode)

SysClk (half frequency mode)

SysClk (half frequency mode)

SysClk (half frequency mode)

ALESet-up to SysClk falling

ALEHold from SysClk falling

Clock LOW Time(5)

Pulse Width(5)4*t22

Clock HIGH Time(5)

Clock LOW Time(5)

t22-2

t22+2

t22-2

t22+2

ns

4*t22

4*t22

4*t22

4*t22

ns

2*t22-2 2*t22+2

2*t22-2 2*t22+2

ns

2*t22-2 2*t22+2

2*t22-2 2*t22+2

ns

9

—

8

—

ns

2

—

2

—

ns

t38 A/DSet-up to ALE falling

10

—

9

—

ns

t39 A/DHold from ALE falling

t40 WrSet-up to SysClk rising

t41 WrHold from SysClk rising

t42 ClkIn (1x clock mode)

Pulse Width HIGH(6)

2

—

2

—

ns

10

—

9

—

ns

3

—

3

—

ns

20

—

16

—

ns

t43 ClkIn (1x clock mode)

Pulse Width LOW(6)

20

—

16

—

ns

t44 ClkIn (1x clock mode)

Clock Period(6)

50

50

40

50

ns

tderate All outputs

Timing deration for loading

over CLD(3, 4)

—

1

—

1

ns/

25pF

NOTES:

2889 tbl 11

1. All timings referenced to 1.5V. All timings measured with respect to a 2.5ns rise and fall time.

2. The AC values listed here reference timing diagrams contained in the R3081 Family Hardware User's Manual.

3. Guaranteed by design.

4. This parameter is used to derate the AC timings according to the loading of the system. This parameter provides a deration for loads over the specified

test condition; that is, the deration factor is applied for each 25pF over the specified test load condition.

5. In 1x clock mode, t22 is replaced by t44/2.

6. In 1x clock mode, the design guarantees that the input clock rise and fall times can be as long as 5ns.

5.5

13

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