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ICS932S208YFLNT

Programmable Timing Control HubTM for Next Gen P4TM Processor

Integrated Device Technology 

ICS932S208

Programmable Timing Control HubTM for Next Gen P4TM Processor

Differential Clock Tristate

To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or

tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during

PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the

corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",

"SRC_Stop" and "PwrDwn" register bit settings.

Signal

CPU[2:0}

CPU[2:0}

CPU[2:0}

CPU[2:0}

CPU[2:0}

Pin PD#

Pin

CPU_Stop Pwrdwn Non-Stoppable

CPU_Stop# Tristate Bit Tristate Bit

Outputs

Stoppable

Outputs

1

1

X

X

Running

Running

1

0

0

X

Running

Driven @ Iref x 6

1

0

1

X

Running

Tristate

0

X

X

0

Driven @ Iref x 2 Driven @ Iref x 2

0

X

X

1

Tristate

Tristate

Notes:

1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

Signal

SRC

SRC

SRC

SRC

SRC

Pin PD#

1

1

1

0

0

Pin

PCI_Stop Pwrdwn Non-Stoppable

PCI_Stop# Tristate Bit Tristate Bit

Output

Stoppable

Output

1

X

X

Running

Running

0

0

X

Running

Driven @ Iref x 6

0

1

X

Running

Tristate

X

X

0

Driven @ Iref x 2 Driven @ Iref x 2

X

X

1

Tristate

Tristate

Notes:

1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"

2. Iref x 6 and Iref x 2 is the output current in the corresponding mode

3. See Control Registers section for bit address

IDTTM Programmable Timing Control HubTM for Next Gen P4TM Processor

18

0743G—01/26/10

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