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810001BK-22LF

FemtoClock™ Dual VCXO Video PLL

Integrated Device Technology 

ICS810001-22 Data Sheet

FEMTOCLOCK™ DUAL VCXO VIDEO PLL

Table 3F. PLL Output Divider Function Table

Input

N1

N0

Operation

0 (default)

0 (default) Output divider N = 4.

0

1

Output divider N = 8.

1

0

Output divider N = 12.

1

1

Output divider N = 18.

Table 3G. PLL BYPASS Logic Function Table

Input

nBP1

nBP0

Operation

0

0

VCXO-PLL mode: The input reference frequency is multiplied by the VCXO-PLL. fOUT = fREF * M.

0

1

Test mode: The input reference frequency is divided by the output divider N and bypasses both PLLs.

fOUT = fREF ÷ N.

FemtoClock Mode: The input reference frequency is multiplied by the 2nd PLL (FemtoClock, MF). The

1

0

1st PLL (VCXO-PLL, M) is bypassed. This mode does not support jitter attenuatiion. fOUT = fREF * MF

÷ N.

1 (default)

1 (default)

Dual PLL Mode: both PLLs are cascaded for jitter attenuation and frequency multiplication.

fOUT = fREF * M * MF ÷ N.

ICS810001BK-22 REVISION A SEPTEMBER 8, 2009

6

©2009 Integrated Device Technology, Inc.

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