ICS527-02 Ver la hoja de datos (PDF) - Integrated Circuit Systems

Número de pieza

componentes Descripción

fabricante

ICS527-02

Clock Slicer User Configurable PECL Input Zero Delay Buffer

Integrated Circuit Systems 

ICS527-02

Clock Slicer User Configurable PECL Input Zero Delay Buffer

External Components

Decoupling Capacitors

As with any high performance mixed-signal IC, the

ICS527-02 must be isolated from system power supply

noise to perform optimally.

Decoupling capacitors of 0.01µF must be connected

between each VDD and the PCB ground plane. The

capacitor must be connected close to the device to

minimize lead inductance.

Series Termination Resistor

Clock output traces over one inch should use series

termination. To series terminate a 50Ω trace (a

commonly used trace impedance), place a 33Ω resistor

in series with the clock line, as close to the clock output

pin as possible. The nominal impedance of the clock

output is 20Ω.

P E C LIN

P E C LIN

CLK1

CLK2

p ha s e is

in d e te rm in a te

P E C L IN

P E C L IN

C LK1

C LK2

CLK1 Feedback

C LK 2 Feedback

Using the ICS527-02 Clock Slicer

First use DIV2 to select the function of the CLK2

output. If DIV2 is high, a divide by 2, low skew version

of CLK1 is present on CLK2. If DIV2 is low, a SYNC

pulse is generated on CLK2. The SYNC pulse goes

high synchronously with the rising edges of PECLIN

and CLK1 that are de-skewed. The SYNC function

operates at CLK1 frequencies up to 66 MHz. If neither

CLK1/2 or a SYNC pulse are required, then CLK2

should be disabled by connecting OECLK2 to ground.

This will also give the lowest jitter on CLK1.

Next, the feedback scheme should be chosen. If CLK2

is being used as a SYNC pulse, or is tri-stated, then

CLK1 must be connected to FBIN. If CLK2 is selected

to be CLK1/2 (DIV2=1, OECLK2=1) then either CLK1

or CLK2 must be connected to FBIN. The choice

between CLK1 or CLK2 is illustrated by the following

examples where the device has been configured to

generate CLK1 that is twice the frequency on PECLIN.

Using CLK1 as feedback will always result in

synchronized rising edges between PECLIN and CLK1

if CLK1 is used as feedback. CLK2 could be a falling

edge compared to PECLIN. Therefore, wherever

possible it is recommended to use CLK2 for feedback,

which will synchronize the rising edges of all three

clocks.

More complicated feedback schemes can be used,

such as incorporating multiple output buffers in the

feedback path. An example is given later in the

datasheet. The fundamental property of the ICS527-02

is that it aligns rising edges on PECLIN and FBIN at a

ratio determined by the reference and feedback

dividers.

Set S1 and S0 (page 2) based on the output frequency.

Lastly, the divider settings should be selected. This is

described in the following section.

Determining ICS527-02 Divider Settings

The user has full control in setting the desired output

clock over the range shown in the table on page 2. The

user should connect the divider select input pins

directly to ground (or VDD, although this is not required

because of internal pull-ups) during Printed Circuit

Board layout, so the ICS527-02 automatically produces

MDS 527-02 F

3

Revision 022806

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

Share Link: